Week In Review: Design, Low Power

Tools
Andes Technology certified Imperas reference models for the complete range of Andes IP cores with the new RISC-V P SIMD/DSP extension. The reference models can be used to evaluate multicore design configuration options for SoC architecture exploration and support early software development before silicon prototypes are available.

Cadence’s digital full flow was optimized and certified for the UMC 22ULP/ULL process technologies, which target ultra-low power consumer, 5G, and automotive applications. UMC also replaced its incumbent library characterization tool with Cadence Liberate Characterization.

Ansys released a version of its electronics simulation tools for students. The Electronics Desktop Student provides free access to the electronics product line, including HFSS, Maxwell, Q3D Extractor, and Icepak, to aid in work with antenna, RF, microwave, PCB, IC and IC package designs. Earlier offerings have made the Mechanical, Fluids, Discovery, and SCADE products free for student use. Courses in the tools are also available through Ansys.

IAR Systems’ Embedded Workbench C / C ++ development tools now support Fraunhofer IPMS’s ISO 26262 ASIL-D ready certified RISC-V processor core EMSA5-FS. The companies noted that the pre-certified toolchain simplifies later certification processes. The core is marketed by CAST.

Electronic System Design industry revenue increased 17% to $3.2B in the first quarter of 2021, according to the ESD Alliance. The four-quarter moving average rose 15%, the highest annual growth since 2011. CAE, PCB & MCM, and SIP revenue rose 14.0%, 15.3%, and 12.9% respectively, while the IC physical design and verification segment surged 34.4% compared to the same quarter last year. Hiring in the industry continues, with a 6.7% headcount increase in tracked companies compared to Q1 2020 and a 1.1% increase compared to the previous quarter.

FPGA
Achronix will no longer be going public through a merger with special-purpose acquisition company ACE Convergence Acquisition Corp. after the two parties mutually called off the deal. The proposed merger was contingent on the satisfaction of certain closing conditions including regulatory approvals, which the companies said is no longer feasible under the original timetable of this month. Achronix president and CEO Robert Blake said the FPGA and eFPGA company “remains committed to pursuing additional options to become a public company.”

Xilinx debuted its Versal HBM adaptive compute acceleration platform (ACAP), which integrates HBM2e DRAM to provide 820GB/s of throughput and 32GB of capacity. It also includes 5.6Tb/s of serial bandwidth with 112Gb/s PAM4 transceivers, 2.4Tb/s of scalable Ethernet bandwidth, 1.2Tb/s of line rate encryption throughput, 600Gb/s of Interlaken connectivity, and 1.5Tb/s of PCIe Gen5 bandwidth with built-in DMA, supporting both CCIX and CXL. It targets compute intensive, memory bound applications for data center, wired networking, test and measurement, and aerospace and defense.

Communications
Mobix Labs acquired Cosemi Technologies. Cosemi’s IP and patent portfolio includes a range of hybrid active optical cables (AOCs), optical transceivers and optical engines for connectivity in a range of applications, while Mobix focuses on wireless connectivity with CMOS-based mmWave beamformers, antenna solutions, and RF semiconductors. “It is with great enthusiasm that we welcome the entire Cosemi team to our Mobix Labs family,” said Fabian Battaglia, CEO of Mobix Labs. “Our combination joins together the disruptive technologies of two pioneering companies into one ultra-low latency solution we are calling True Xero that bridges the gap between wired and wireless applications, allowing us to bring our innovations to a wide variety of 5G use cases, from autonomous driving to advanced robotics and everything in between.” Based in Irvine, Calif., Cosemi was founded in 2006. Terms of the deal were not disclosed.

The MIPI A-PHY v1.0 specification was adopted as an IEEE standard, IEEE 2977-2021. A-PHY is the first asymmetric, industry-standard, long-reach, SerDes physical layer interface for automotive applications. MIPI Alliance chairman Joel Huloux noted this was the first time the organization had sought adoption of its specifications by another standards body.

Security
Accellera published the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0. Developed by the IP Security Assurance (IPSA) Working Group, the new standard defines a specification that documents security concerns for hardware IP and its associated components when integrated into an IC, allowing IP providers to either identify security concerns to mitigate within their IP or disclose the concerns to their integrator. The standard is design, product, and tool independent and is available at no cost.

Infineon Technologies and IDEX Biometrics teamed up on a smart payment card reference design that uses fingerprint biometrics for identity verification. The card implements Infineon’s SLC38BML800 security controller with additional GPIO-interfaces and the latest generation of the TrustedBio solution from IDEX Biometrics.

Memory
SK Hynix began mass production of 8 Gb LPDDR4 mobile DRAM based on 1anm, the fourth generation of 10nm process technology. SK Hynix expects 1anm to result in a 25% increase in the number of DRAM chips produced from the same size of a wafer compared to the previous node. The technology will also be used for its DDR5 products next year. This also marks the first time the company is using EUV in mass production.

Tsinghua Unigroup is filing for bankruptcy with a plan to restructure. Among the subsidiaries the conglomerate owns are mobile chip designer Unisoc as well as flash memory manufacturer Yangtze Memory Technologies Co (YMTC). Creditor Huishang Bank requested the bankruptcy filing.

Quantum computing
Duality, an accelerator focused on quantum computing startups, accepted six companies for its first program. The selected startups will receive $50,000 as well as mentorship and business training from the University of Chicago. The companies are: Axion Technologies (quantum random number generator for HPC), Great Lakes Crystal Technologies (manufacturing semiconductor-grade diamond materials), qBraid (cloud-based quantum management platform), QuantCAD (simulation software for noise in quantum devices), Quantopticon (simulation software for quantum optical devices), and Super.tech (quantum computing application optimization).

QuantWare released a commercially-available superconducting processor for quantum computers. The 5-qubit QPU is targeted at research institutions and universities, and the company said it has 99.9% single-qubit gate fidelities for manageable error rates. QuantWare also reported pre-seed funding of €1.15M (~$1.4M).

BMW Group is hosting a contest that challenges participants to develop quantum algorithms that can be applied to the automotive industry. In particular, the focus areas are optimization of sensor positions for automated driving, material deformation simulation, pre-production vehicle configuration, and machine learning quality assessment. AWS is offering credits for Amazon Bracket so entrants can test solutions. BMW Group said it will become a client of the winners.