Week In Review: Design, Low Power

Tools
OneSpin launched a formal verification tool that integrates with all major simulators, coverage databases and viewers, and chip design verification planning tools to provide a comprehensive view of verification progress. Comprised of two new formal apps, it can identify unreachable coverage points and provide them to the simulator to reduce wasted effort.

Synopsys released the latest version of its FineSim SPICE circuit simulator for analog design. Improvements include faster simulation of large, advanced-node designs containing a massive number of post-layout parasitic elements as well as RF-class analysis capabilities to support high-frequency analog circuits. Synopsys’ Custom Compiler design tool also saw a new release that added performance improvements as well as features for early signoff-quality parasitic feedback during the design process and signoff-quality DRC during layout.

Mentor added new technology to its Tessent product that creates an industry-standard interface for communication between proprietary, tester-specific software and DFT platforms. ATE-Connect provides IJTAG commands to the device under test and receives data from the device on the ATE while protecting sensitive design information. Teradyne’s UltraFLEX test solution supports the new interface through its PortBridge technology.

Cadence’s custom and analog/mixed-signal tools were certified for Samsung Foundry’s 7nm Low Power Plus (7LPP) process technology. The company’s full-flow digital and signoff tools have also been certified for the process.

IP
eSilicon launched its 7nm neuASIC IP platform for customer AI ASIC designs. The platform includes compiled and hardened 56G SerDes, HBM2 PHY, and AI mega/giga cells, including convolution engine and accelerator builder software. The library of AI-targeted functions can be combined and configured to create custom AI algorithm accelerators.

Synopsys uncorked memory interface IP supporting DDR5 and LPDDR5 SDRAMs. The LPDDR5 controller, PHY, and verification IP supports data rates up to 6400 Mbps with up to 40% less area than previous generations, while the DDR5 IP solution supports up to 4800 Mbps and can interface with multiple DIMMs per channel up to 80 bits wide.

Cadence debuted long-reach 112G PAM-4 SerDes IP in 7nm. Based on technology gained from Cadence’s 2017 acquisition of nusemi inc, the 112G SerDes supports backplane, copper and optical connections and includes a firmware-controlled adaptive power design, multi-rate support, and autonomous startup and adaptation.

eSilicon’s long-reach 7nm 56G DSP SerDes is now available for licensing. It provides error-free operation in 56G PAM4 over a 30dB backplane without forward error correction. A GUI provides access to monitoring features such as non-destructive eye diagrams, SNR & BER, bathtubs, histograms and power measurements.

Arm added access to the Cortex-A5 CPU, a low-power, Linux-capable application processor, as part of its DesignStart program. The program provides a simplified contract with access to the IP and one year’s support for $75k.

Numbers
UC Berkeley’s startup accelerator Berkeley SkyDeck is launching a chip track in Spring 2019 that will offer dedicated resources including MPW wafer runs,  access to experts, and $100k in investment to startups focused on semiconductor design and related technologies. Cadence, TSMC, and SiFive are supporting the program. Two companies will be selected every six months; applications are open until Nov. 7.

Cadence released third quarter financial results with revenue of $532 million. On a GAAP basis, the quarter saw income of $0.35 per share, and non-GAAP income of $0.49 per share. The company is using new reporting rules; under the previous rules, revenue was $526 million for Q3 2018, up 8.5% from the same quarter last year. GAAP income per share was $0.34 for the quarter, up 17.2% from $0.29 in Q3 2017, while non-GAAP income per share was $0.49, up 40% from $0.35 per share. Alongside increasing stock repurchases, the company is raising its outlook for the year and expects total revenue in the range of $2.113 billion to $2.123 billion.

Events
There’s a new show in town. Next year, the ESD Alliance will present ES Design West with a focus on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Co-located with SEMICON West, it will be held July 9-11 in San Francisco, CA.

Linley Fall Processor Conference: Oct. 31 – Nov. 1 in Santa Clara, CA. Focused on processors for communications, IoT, servers, and advanced automotive systems, the conference features a number of sessions on AI architectures as well as a keynote covering technology and market trends.

ICCAD: Nov. 5-8 in San Diego, CA. The technical conference focused on emerging technology challenges in EDA features keynotes on IoT and Cloud systems, DARPA’s Electronics Resurgence Initiative, and the impact of technology trends on EDA tools and flows. Special sessions, tutorials, and workshops are also part of the program.

IEEE Rebooting Computing Week: Nov. 5-9 in Tysons, VA. The first two days will focus on the International Roadmap for Devices and Systems, while the International Conference on Rebooting Computing will be held the 7-9^th. The conference focuses on novel computing approaches, including algorithms and languages, system software, system and network architectures, new devices and circuits, and applications of new materials and physics.

Phil Kaufman Award Ceremony and Dinner: Nov. 7, 6:30 – 9:30 p.m. in San Jose, CA. This year’s award honors Thomas W. Williams for his contributions to test automation including Level Sensitive Scan Design and subsequent enhancements to IC testing including adaptive scan.

RISC-V Summit: Dec. 3-6 in Santa Clara, CA. The first annual conference and exhibition dedicated to the RSIC-V ISA ecosystem. Training sessions, workshops, and presentations will be available, followed by a day for Foundation members.