Week In Review: Design, Low Power

Tools & Standards
Mentor uncorked a PCB design platform for non-specialist PCB engineers focused on multi-dimensional verification. The Xpedition platform can integrate a range of verification tools within a singular authoring environment, providing automatic model creation, concurrent simulation, cross probing from results, and error reviews to identify problems at the schematic or layout phases.

Aldec added VHDL-2018 interfaces and automatic coverage model generation to its Riviera-PRO verification platform. Early support includes conditional compilations, conditional expressions in declarations, constraint inferral (from initial values), and bidirectional connections.

Accellera published the UVM 2017-1.0 reference implementation. The latest version aligns it with the new IEEE 1800.2 standard and addresses some inconsistencies between the UVM Register Layer and other standards, according to UVM Working Group chair Justin Refice.

IP
Spin Memory is teaming up with Arm to create SRAM-class magnetoresistive random-access memory (MRAM) design IP based on Spin Memory’s Endurance Engine design architecture. The embedded MRAM design IP will address SRAM application in SoCs, with denser and lower power solutions than typically achieved with the current 6T SRAM cell-based IP. Spin Memory, formerly known as Spin Transfer Technologies, is also working with Applied Materials on bringing the technology to market in 2019.  The company recently completed a $52 million Series B funding round led by Arm and Applied.

Achronix launched two programs to boost access to its eFPGA technology. The first, aimed at universities, government agencies, and industry consortia, allows researchers to use preconfigured Speedcore eFPGA IP to build programmable hardware accelerators into their SoC research projects. The second, aimed at companies, allows them to incorporate preconfigured eFPGA IP into their ASICs and SoCs for evaluation volume fabrication.

Imagination announced the PowerVR Series8XT-A GPU core aimed at automotive applications, particularly cluster, HUD, infotainment, and ADAS functions. It includes built-in hardware virtualization as well as recovery and reliability features such as ECC and LBIST to ease automotive safety certification.

Mipsology integrated its Zebra neural network acceleration technology with Mellanox Technologies’ Innova-2 Flex SmartNIC for neural network inferencing at the edge. Mipsology’s software stack sits on top of Xilinx FPGAs; in benchmarks using ResNet50, the company’s accelerator processed 2,000 images per second using the Xilinx Alveo U200 and 3,700 images per second on Xilinx Alveo U250. It also runs on Advantech’s VEGA-4001 acceleration boards, which on two Xilinx VU9P FPGAs with 32GB DDR memory and a 16x PCIe interface reached 25,000 images per second using CaffeNet.

Arasan Chip Systems launched MIPI M-PHY IP supporting Gear 4 speeds of upto 11.6gpbs. The M-PHY IP is integrated with the company’s JEDEC UFS 3.0 Host IP and UFS 3.0 Device IP Controller Cores.  A Linux based UFS 3.0 Software Stack and UFS 3.0 HDK are available to accelerate prototyping.

Deals & Certifications
Cadence’s advanced packaging design and analysis tool flow was certified by Samsung Foundry for its Fan-Out Panel-Level-Packaging (FO-PLP) and silicon-interposer 2.5D package. The flow was verified with memory interfaces, high-speed interfaces and a core Power Delivery Network for CPU and GPU.

Esperanto Technologies selected Moortec’s 7nm embedded in-chip PVT monitoring subsystem IP to optimize performance and increase reliability of its RISC-V based AI Supercomputer-on-a-Chip.

Achronix will use Micron’s GDDR6 memory for its next-generation stand-alone FPGA products on TSMC 7nm process.