What Works After 7nm?

An Steegen, senior vice president of process technology at Imec, the Belgium-based R&D organization, sat down with Semiconductor Engineering to discuss the future of process technology and transistor trends all the way to 3nm.

SE: Some say the semiconductor industry is maturing. Yet we have more device types and options than ever before, right?

Steegen: Indeed, the application space is growing. You have the IoT, new devices and the cloud. Each of these applications has different specs. So there are many applications that need some type of technology. And so there are a number of options that are opening up. Look at memory today. You have the conventional hierarchy. But you have a latency gap, where storage-class memories could come in. Then you have the IoT for ultra-low power applications. That could be a reuse of 28nm or 40nm technologies.

SE: What about leading-edge technology?

Steegen: For cloud computing and servers, the demand is growing too. That is, of course, where leading-edge technology needs to come in. That doesn’t disappear.

SE: But chip scaling is becoming more difficult and costly at each node. What are the challenges and how does the industry deal with them?

Steegen: The question is how do you manage cost if the nodes are getting more complicated. At every node you have to do this in a cost effective way. Of course, if you look at multi-patterning and other technologies, your process cost is definitely going up. Then you look at the transistor cost or cost per transistor. There is, of course, a process cost that goes into that. Are there ways to offset that? I can scale the area more aggressively. I can also look at my design. I can do metal track scaling. So a combination of dimensional and metal track scaling can give you an aggressive scaling path. Or you can relax the cost of multi-patterning a little bit by combining these two. This is a smart way of managing your cost. You must have this type of mindset to make sure that you manage the cost per transistor moving to the next nodes. It’s a very high focus, even for us today in R&D, so we look at it from that angle.

SE: R&D costs are also going up, which is partly responsible for consolidation in the industry. How does the industry deal with that?

Steegen: The whole industry is changing. Look at the suppliers. There is consolidation. This impacts R&D and R&D consortia. I can only speak for Imec. At Imec, R&D cost sharing is important. One of the reasons we have this type of business model is because R&D costs are increasing. So how we share the cost is important. That’s one thing. The other one is also in the pre-competitive space. You basically want to bring all of the players together. That way, the entire ecosystem knows what to do and so everything is ready on time. That is a key role that Imec basically needs to fulfill. For Imec, we need to be on top of the roadmaps. We need to be on top of where the problems are and looking at the possible solutions. The pathfinding and the timelines are very critical. This comes with hard work and with many people looking at it.

SE: What are the challenges on the device side?

Steegen: For us, it’s continuing to make progress on scaling. We must make sure that we can continue to deliver power, performance and area. It’s becoming more complicated at every node. For example, the industry is moving towards finFETs as a high-performance device. Any of these big disruptive changes take time. But it has been proven that the finFET is a good performing device at a lower Vdd. Now the big challenge is pushing the finFET to the next thing.

SE: What’s the next thing?

Steegen: The question is how far can you push the finFET. One way you can get more performance out of finFETs is to make the fins taller, because you can get more current through it. But if you make it taller, you may have more RC, or a resistance-capacitance, penalty. The question is, ‘Can you overcome it?’ That’s the main question for the next-generation of finFETs.

SE: How far can you scale the finFET?

Steegen: It all depends on how much you push the fin dimensions. Today, we are already working on finFETs with fins that are 5nm wide. Now you can say you can scale them to 4nm. But there are not many nanometers left here to scale the finFET.

SE: Then what happens?

Steegen: At some point, this process is going to break. At some point, the finFET is not going to scale anymore. At Imec, we are looking at when this could happen and at what dimensions. And, of course, we are looking at the alternatives for that generation. That’s why we are focused on nanowires, which is another way of managing your electrostatics of the device. We also are trying to do this in the most cost-effective way. So we are looking at migrating the process flow from a finFET to a nanowire or a lateral nanowire FET. We are looking at how to control this process. Those are some of the next items to tackle.

SE: Foundries are shipping 16nm/14nm finFETs, with 10nm finFETs in development. Based on Imec’s roadmap, there are two transistor options at 7nm—the finFET and the lateral nanowire FET. So what happens at 7nm?

Steegen: There are a lot of discussions about 7nm. Will the finFET last for one more node and scale to 7nm? Or will you have to do the next thing? And the next thing is likely the lateral nanowire, because it gives you more of a window on the electrostatics of your device. You don’t have to scale the width of the nanowire as aggressively as you would have to for the fin.

SE: Have the foundries made up their minds in terms of moving to finFETs or nanowire FETs at 7nm?

Steegen: I can’t speak for other companies. They should already know where they are heading. That’s all I can say.

SE: When will 7nm happen?

Steegen: As far as where I am at today, 2017 is likely for N7. That’s early production or qualification. Of course, it doesn’t end there. That’s where your yield ramp starts.

SE: The lateral nanowire FET may appear at 7nm or 5nm. Can you describe the lateral nanowire FET?

Steegen: The nanowire FET is a gate-all-around device. You have a fin. The gate wraps around it. The nanowires are stacked. The current of the fin is equivalent to the proportion of the width. If I have one nanowire, that’s not enough. You need many nanowires stacked to outperform a finFET.

SE: Is the lateral nanowire FET a revolutionary step from the finFET?

Steegen: It’s an evolutionary migration from a finFET. This means that it’s not a disruptive or a completely drastic change from a finFET. Vertical nanowires, for instance, would represent a drastic change. Tooling wise, the lateral nanowire FET can be manufactured with the equipment that is there today. Do you remember the early days of bulk finFETs? One of the big concerns was how can you control the shape of the fin. People have figured that out by now. So that’s the next question for the nanowire. How can you control the nanowires? What is the metrology you have to use? How do you tweak your processes to have better control? So, it’s all about control, such as your cleans and metrology. In addition, RC management is also very important.

SE: What channel materials will be used for a nanowire FET? Will III-V play a role?

Steegen: One of the differences between germanium, silicon-germanium and III-V is that the epitaxial growth for III-Vs is way more challenging. To control the defects, III-V has proven to be more challenging. That’s one thing. The second thing is that you don’t combine two difficult things at the same node. So combining a nanowire and III-V material is, of course, a very big step. In my opinion, it’s not going to happen at the same time. III-V readiness needs to mature further. That will likely get pushed out.

SE: How far can we scale the lateral nanowire FET?

Steegen: When you change to a new architecture, you really want to keep it for two nodes, preferably three. One way to scale this is to stack more nanowires. So let’s say in the first node, you have three wires. Then, you go to four or five.

SE: What are you looking at for the 3nm node?

Steegen: We are looking at vertical FETs and different switching mechanisms like tunnel FETs. We are also looking at spin devices, which can be added to CMOS. You can have some functionality added by putting a spin wave on it. These are the combinations we are looking at. So what you are likely going to see is what we call hybrids. It’s a CMOS technology, maybe augmented with a specialty device. Or you might have some design innovations, such as reducing the metal tracks on a device. So you are going to see combinations of these things coming in to get a node-by-node power, performance, area, and at a cost number where you want them to be.

SE: What about other technologies like fully depleted silicon-on-insulator (FD-SOI) and quantum-well devices?

Steegen: Quantum-well devices may come in when you bring in high-mobility materials. It’s always an option you keep open. FD-SOI is very attractive for 28nm or 22nm. This is for low-power applications like the IoT.

SE: The industry hopes to insert EUV at 7nm. What’s the progress with EUV?

Steegen: There is steady progress. That’s clear from the data we see. Is the ecosystem ready? This involves the source, resists and the mask. There is also steady progress there.

SE: What other tools and materials are critical at advanced nodes?

Steegen: Conformal films are key. Interface treatments are important. In the backend, low-k treatments are critical. Self-alignment is also very important. How do you self-align features to each other? You may need to have selective deposition. That’s what I want to say for the backend. If you can selectively treat your surface with some of these materials, you can selectively grow and deposit these materials.

SE: What else?

Steegen: If you look at the roadmaps, there are so many small and big innovations that are needed. You cannot pin it to one. The fact that EUV is needed is clear. We also need the right ALD materials. The dimensions are so small. So how you basically build the stacks on top of each other is critical. And when you are in the nanometer-scale, you need to have the right metrology.