Why Use A Package?

Subramanian Iyer, distinguished chancellor’s professor in UCLA’s Electrical Engineering Department—and a former fellow and director of the systems scaling technology department at IBM—sat down with Semiconductor Engineering to talk about the future of chip scaling. What follows are excerpts of that conversation.

SE: Advanced packaging is being viewed as a way to extend scaling in the future. What’s your view?

Iyer: There are a few key things happening. One is that the architecture of systems is becoming very heterogeneous. The classical von Neumann computers are not going away, but they are going to be augmented by non-von Neumann machines, which require much more intimate memory-processor interconnect than we have seen so far. Neuromorphic computing and cognitive computing all will benefit immensely from the breakdown of the von Neumann paradigm. Second is that systems are getting cyber-physical. They’re no longer just electronics. They’re electronics with sensors and MEMS. Heterogeneity is becoming very important. And the other thing that’s happening is that the cost of SoCs has gone up tremendously.

SE: What kind of numbers are we talking about?

Iyer: The non-recurring engineering charge for a new fairly basic SoC is, at a minimum, $30 million to $50 million. For a big processor type of SoC, it’s $500 million to $1 billion. There has been a big consolidation in the design space, with the biggest being Avago-Broadcom. But there are many others happening. So if you go back to Silicon Valley and look at how many startups are there, the answer is very few. The reason is it takes three to five years to build an SoC, it takes $30 million to $50 million at a minimum, and nobody is willing to put their money into something that’s so risky. By the time you get your chip back, the market may have evaporated.

SE: What does this mean for Moore’s Law?

Iyer: That has been the model for shrinking features in a silicon chip. But if you look at the board and the package, those have not shrunk much in the last 50 years. If you go back to the late 1950s, we were making 15 micron features. Today we’re making 15 nanometer features. But in the late 1960s, the pitches were about 395 microns. Today our pitches are about 150 microns. And if you look at any other packaging metric, whether it’s bump pitch, BGA pitch, they have not scaled that much. This is not a holistic interpretation of Moore’s Law. If you think about the system as a whole, then shrinking the package and the board has got to be an integral part of Moore’s Law. That’s what we’re trying to do here at UCLA.

SE: So what changes and what remains the same?

Iyer: Any time you build a new SoC, you’re basically taking everything that has previously been done, and doing it again on a piece of silicon and interconnecting it all. About 90% of an SoC has existed in some form before. The remaining 10% is the secret sauce. Another important part is how you interconnect them. We’re taking very complex SoCs and breaking them up or fragmenting them into small pieces.

SE: Is this hard IP or soft IP?

Iyer: We’re going to make these pieces hard IP. These are die-lets. Today you use soft IP and re-synthesize it. We’re saying you don’t have to re-synthesize it. We can use hard IP and reconnect it into an SoC. The catch is that it has to be reconnected, and today there is no simple way to do that. Bump pitches are 50 microns, and the connections on a chip are between 2 and 10 microns. We have to shrink the interconnect pitches down to 2 to 10 microns so they are the same dimension as the wiring on a silicon wafer.

SE: How do we do that?

Iyer: That’s one of the big technology projects. We’re looking at it. But the other question is why hasn’t this been done in the last 40 to 50 years? The reason is that there was no need. The need to go off chip became less and less, and when we did we were rescued by SerDes—the serializer/deserializer. At a great cost in energy and space, it allowed us a very high data rate over a single channel. Even though we were limited by the number of I/Os that could escape a chip, we made up for it by sending signals through that chip at very, very high speed.

SE: What’s the overhead on that?

Iyer: SerDes speed has been going up exponentially. If you look at a chip today, about 25% to 30% of the area is SerDes. But 25% to 30% of the power is also SerDes. It’s like the courier on a board.

SE: Is there a better way to improve the interconnect?

Iyer: We can make them highly parallelized without necessarily going to higher-speed interconnects. That lowers the power and the area requirements.

SE: Then what happens to the package?

Iyer: You have to ask yourself, what is this package really doing? It has a number of major functions. One is that it’s supposed to protect the chip. That assumes the chip is a very delicate thing and you need to put it into a package to protect it. However, with the advent of low-k dielectrics and so on in the back end, the package has become a big problem. It has so many different kinds of materials on it that its coefficient of thermal expansion is quite complicated. When the chip goes up and down in temperature by even a few degrees, it creates enormous pressures on the chip and causes the chip to cohesively fail, especially with low-k dielectrics. That’s commonly called chip-package interaction, and it’s a major problem today in chip packaging. The second thing it does is protect the chip thermally, or at least it’s supposed to. But it doesn’t really do that. If you look at where heat goes from the chip, it goes through the heat sink, which is mounted directly on top of the chip. Then the heat cannot escape through the package because the package is usually organic and doesn’t conduct. I would argue the package doesn’t protect the chip mechanically or thermally. The package also allows the chip to communicate with other chips. However, it does it inefficiently. Basically it’s taking some very fine-pitch wires on a silicon chip and fanning them out to get to the BGA pitches so you can mount it on a board, and then connect it to another BGA using tracers.

SE: Is there anything the package does well?

Iyer: It allows us to test the chip. That function it does quite well. Anything that gets rid of the package needs to comprehend how we’re going to test these die at full spec.

SE: So what happens without a package?

Iyer: You get rid of a huge amount of space. The dimensions are about 3X on each side of a chip. For a high I/O type of chip, the package area is about 10X the chip area. If you get rid of that, you reduce the footprint of the die to a fraction of what it used to be on the board. The problem is that the board pitches are BGA pitches, which are not even measured in microns. They’re measured in fractions of millimeters. How do you take a board dimension and shrink it down to 2 to 10 microns? The answer is you have to rethink the board. The way boards are designed today they have to be big, and because they’re big they’re very expensive. So you use the cheapest material you can get. That has been the other Achilles heel of packaging. It has not been viewed as adding value. It was limited to a cost center. That’s why the whole OSAT business took off. Their focus was getting the cost out.

SE: So how do you make those pitches fine enough?

Iyer: By replacing the board with a silicon wafer. In the 1960s, Gene Amdahl had this idea of building an entire mainframe system on one wafer. The problem is he couldn’t get enough yield on a four-inch wafer. That led to the SoC. What I’d like to do is to take a very big system—think of it as an SoC the size of a wafer. It has memory, different types of processors, DRAM, SRAM, non-volatile, FPGAs, RF. Think of everything on one giant chip. You start with that system, but it’s like one big silicon chip. There are no SerDes — or at least they’re not the same kind of SerDes. They’re much more efficient because they’re small. And there are a lot of parallel connections because wires on a chip are relatively cheap. Now you break up this chip into die-lets that are of the order of 1 millimeter to a few millimeters in size. There are thousands of these making up your system. They are very easy to manufacture, and 90% or them are used in every SoC we have today. You could make tons of these very cheaply and stock them.

SE: Does this make them more reliable?

Iyer: In one sense, yes, because you can optimize the technology for each die-let. They don’t all have to be made in 14nm technology. Some can be done at 130nm. By minimizing the number of die-lets made in the latest technology, you minimize the reliability exposure. You also are no longer beholden to one supplier.

SE: Does it make it easier to develop chips?

Iyer: Yes. This is comparable to the application software space today. If you get a brilliant idea, you go to Apple or Google and download all of the objects, put them together, and it produces an app. The next day people are downloading that app. It may cost a couple thousand dollars. If it doesn’t work, it’s not a big deal. We need to transform Moore’s Law into a system. What is the most efficient way to pack more functionality into a system per dollar.

SE: What does this do to your bill of materials? And is it harder to manage?

Iyer: The supply chain does become more complicated. Now you have to track a lot of parts. If you’re building a router and you have one or two big SoCs, you can build a system with a few chips. Now you may have thousands of parts and you need to make sure the integrity of the supply chain is intact. But 90% of these parts are general-purpose. I expect there will be small assembly operations. We will have 90% of these die-lets on-site at these assembly houses or in central warehouses. If you want to put a system together, it may cost $300k and 90% of the die are already available. You can add an interconnect fabric to put all of this together. Another 10% of the die-lets don’t exist, and you will have to develop them. So it may cost you another $200k and you can get it manufactured anywhere. That’s your secret sauce. You want to design those things.

SE: What’s the interconnect fabric?

Iyer: That’s the million-dollar question. We need an interconnect that can, at a reasonable cost, produce two to four layers with a 2- to 10-micron pitch. We want this material to be thermally conductive, because we want to take heat from both sides. We want it to be rigid and tough. The material that fits all of those criteria is silicon. The hardcore packaging guys say silicon is expensive, plastic is cheap. But the cost of these things is not materials. It’s the processing. Today, even if you strain the limits, you can get 5 micron lines and spaces on plastic, but the yield will be about 1%. So 90% of the cost is making the wires and making the connections. It’s much easier to do that on silicon than on organic materials.

SE: What’s the difference between this and a silicon interposer?

Iyer: An interposer doesn’t eliminate the package. I was one of the first to build a real product on an interposer. Interposers and 3D are like half-steps, and you’ve added additional complexity. And you can’t shrink the pitch much, so you’re stuck at 40 to 50 microns.