Power integrity optimization can no longer be a reactive step in the backend process.
At DesignCon in January, I was a panelist at a panel session entitled “Power Integrity For 10nm/7nm SoCs – Overcoming Physical Design Challenges And TAT.” I was on the panel together with Arvind Vel, Sr. Director Applications Engineering, ANSYS, Inc. and Ruggero Castagnetti, Distinguished Engineer, Broadcom Limited. This topic is of course extremely broad, but it was interesting getting feedback from different angles of the industry.
One of the most eye-opening moments was when Arvind Vel got a question from the audience: “Looking at the transition to 10nm and 7nm; from your customer interaction, what are yours and ANSYS’ experiences on the biggest surprise that customers see when arriving to those process nodes?” His answer was… routability. Not DVD, not noise, not EMI or thermal. Routability! In particular, those customers who skipped the 10nm node and are moving directly to 7nm could be in for a big, and fairly unpleasant, surprise.
I would second that experience based on my own customer interaction. And it underlines the complexity that physical designers are challenged with today compared to just a few years back: the boundaries between the traditional steps of a physical design flow – placement, CTS, routing, post-route optimization – are breaking down, and you need to design for routability and timing closure as early as the power grid creation stage.
This realization calls for different approaches – holistic approaches – and different flows than what exists today. Power integrity optimization needs to be taken in as a proactive step at the floorplanning / power grid stage instead of a reactive step later in the backend process.
In many ways it’s a margins game, in the sense that you need to make sure that you have optimized for enough implementation margins early in your physical design flow to achieve convergence at the end of the flow. And this without leaving money – in terms of implementation head room – on the table. This includes using a power integrity optimization tool like FloorDirector to build a CAD flow which is robust at 10nm and 7nm designs, as well as requiring a concurrent design effort by routing, power integrity and placement experts.
10nm and 7nm means a need to work closely together in multi-disciplined approaches and crossing the boundaries of traditional design flow steps, in order to allow for design convergence and timing closure. It also means that over-the-wall delivery, e.g. from a team in the US to another in India, is very challenging, and will put stress on some of the existing organization structures built around the traditional siloed flow. Interesting times indeed! How is your CAD flow doing in this new reality?