10nm And 7nm Routability – How Is Your CAD Flow Doing?

At DesignCon in January, I was a panelist at a panel session entitled “Power Integrity For 10nm/7nm SoCs - Overcoming Physical Design Challenges And TAT.” I was on the panel together with Arvind Vel, Sr. Director Applications Engineering, ANSYS, Inc. and Ruggero Castagnetti, Distinguished Engineer, Broadcom Limited. This topic is of course extremely broad, but it was interesting getting fee... » read more