After Moore’s Law: Dwindling economic benefits will change the landscape for semiconductor, design and EDA companies.
During DAC 2013, Robert Colwell of DARPA said he was attempting to prepare the U.S. Dept. of Defense for what he believes is the cataclysm caused by the end of Moore’s Law. He asked the question, “What happens when we don’t have a new technology that doubles the number of transistors every couple of years?”
Colwell believes that power is the primary reason why Moore’s law will stop and his prediction is for 2020 and 7nm. He also cited fab costs as being a near-term limiter.
Regardless of whether the end of Moore’s Law will be cataclysmic, it is certainly true that it will have a significant impact on the design of systems and the IP industry. It is interesting to note why he believes it to be significant for national security. His reasoning is based on the assertion that if the United States cannot stay ahead of the rest of the world in terms of compute power and other such technology trends, then the rest of the world will be able to become as technologically capable as the United States and either be able to do things without the U.S. government being able to find out, through spying and other types of information gathering, or that the rest of the world will be able to find out what the United States is planning to do.
People may not agree with his assertion or the ethics implied by it. In fact, Semiconductor Engineering believes design will become more important than in the past (see After Moore’s Law: More With Less). Design and the selection of the optimal architecture will be necessary to increase performance or to reduce power. And design will become a way to differentiate more than it has in the past, separating the winners from the losers.
Semiconductor Engineering asked the engineering community who they thought the winners and losers would be in a world without Moore’s law and what changes have to be made to become a winner. The consensus is that if the industry cannot rely on technology scaling to reduce costs, the winners will be:
“Arguably, Moore’s law has made us lazy,” says Bernard Murphy, CTO at Atrenta. “We will have to lean on architecture and design ingenuity again.”
One way to reduce costs is by improving the system assembly process. “We must provide true system-by-assembly, so the developer can simply plug in the desired collection of IP cores and IP subsystems with complete confidence that they will work together,” says Drew Wingard chief technology officer of Sonics, Inc..
Along with assembly, better analysis tools are required. “We can expect to see more tools that make it easier and faster to bring IP together,” says Bob Smith, senior vice president of marketing and business development for Uniquify, Inc.. “This will enable modeling of the system behavior and performance very early on in the development cycle.”
The creation of better tools enables designers to do their jobs better. “Chip architects now fully embrace the idea that their value-add is centered on their mastery of the system issues,” says Chris Rowen, a Cadence fellow. “They understand the application-centric, differentiated design and integration of all the necessary hardware, software and interfaces to make real solution platform for their customers.”
Another way to reduce costs is by understanding and responding to customer needs. “Companies with tighter access and ties to the customer have an advantage,” says Patrick Soheili, vice president and general manager for IP solutions and vice president for business development at eSilicon. “For example, OEMs with captive customers have the opportunity to reduce their COGS, increase performance by tightly coupling system-level software levers into faster, more efficient hardware levers, while protecting their core competencies against competitors.”
Part of that efficiency equation is also understanding how to do more at the same process technology. There is a lot of low-hanging fruit that can be plucked for minimal investment.
“Our hypothesis is that Moore’s Law is dead or dying,” said Kurt Shuler, vice president of marketing at Arteris. “The one-and-a-half-year crank is gone. You need to design chips smarter. So 40nm might exist 10 years from now. Both analog and digital will exist a long, long time at older nodes.”
“It does seem that an IP developer who is trying to gain adoption in an established node is going to have to deliver innovative designs that can directly affect the end customers’ economics,” says Joseph Sawicki, vice president and general manager of the Design to Silicon Division at Mentor Graphics. “Time to market on the advanced node is replaced by time to more money in an established node.”
For an IP supplier, not only do they have to do more with less, but they have to provide additional advantages for their customers. “The trend across hardware and software design right now is to create technologies that free the industry from historical ties to underlying ISAs,” says Alexandru Voica, technology PR specialist at Imagination Technologies. “However, inherent architectural attributes remain important for dynamic compilation performance, how efficiently an architecture implements in silicon, and support for open standards and operating systems.”
It is clear that IP can no longer exist without an ecosystem surrounding it. “IP developers, due to their role in ecosystem enablement, will have a similar experience as EDA companies,” says Ron Moore, vice president of marketing for the Physical Design Group at ARM. “This means prioritized collaborative investment in new process technologies, and long product lifecycles to ensure second- and third-wave adoption.”
“The ROI and risk-mitigation advantages of IP-based design are quite compelling,” says Rowen. “This is especially true as the ecosystems around IP grow, whether it is software ecosystems for CPU and DSP IP, or the verification ecosystems around interconnect and interface IP.”
The ecosystem is rapidly increasing in the software space. “The IP software stack will become a much bigger differentiator,” says George Janac, chief executive officer for EDA Systems. “Can a vendor supply me with the IP, driver, and OS software stack? Clean interconnection schemes will also become very important part of reducing IP integration costs.”
Wingard supports the latter part: “We need flexible on-chip networks that enable the developer to optimize the performance, area and especially power of the SoC to meet the system requirements. IP will need to be optimized for easy integration, providing all of the required modeling and verification views, device drivers, etc.”
Optimization and diversification
But IP vendors not only have to worry about easing the integration issues, they also have to worry about optimizing for specific fabrication processes. “IP developers need to work with the foundry at the early technology development stage to stay competitive in terms of performance, cost and time to market,” says Bruce McGaughy, chief technology officer and senior vice president of engineering of ProPlus Design Solutions. “DFY is certainly one key technology IP developers must consider to ensure the best tradeoff between PPA and yield.”
Charlie Cheng, chief executive officer of Kilopass Technology, is concerned about the diversification of production technologies and the extra load this places on IP suppliers. “When the mixed-signal designers join the party, it will be even more confusing, because there will be additional layers of complexity added for their needs, further fracturing the baseline of technologies from which to innovate from.”
Not all see this as a disadvantage. “Continued innovation in the foundry landscape will continue to create opportunities for IP vendors,” says John Koeter, vice president of marketing for the Solutions Group of Synopsys. “This enables them to develop and differentiate their IP as they seek to meet customer requirements.”
So, who will be the losers in this post Moore’s law world? “FPGA vendors have been protected for over 20 year by being able to move to the next cost reduced node every two to three years,” says Janac. “One path of defense for FPGA companies is the SoC FPGA paradigm, which enable increased content with minimal die increase. Another defense path is bigger devices by interposer stacking, ala Virtex-7 2000T. But a structured ASIC in a 28nm/22nm process could serve many markets at a whole new price point. Even at 40nm.”
The only real conclusion is that the winners will be those who can best adapt to the changing needs of their customers and to help drive down the total cost of design and manufacturing.