Advanced nodes are making voltage drop much worse.
Voltage drop has always been a significant challenge. As far back as 130nm, specialist tools were being used to ensure that enough local decoupling capacitance (decap) cells were inserted in addition to larger decaps implemented around the SoC. But advanced nodes are complicating matters and further increasing complexity.
These technological challenges, which underlie the power, performance and area benefits of scaling, must be solved in order to make semiconductor products a profitable business, said Tobias Bjerregaard, CEO of Teklatech. “Power-related challenges are among the most pressing. Voltage drop results in poor power integrity, and the trend is that this is getting increasingly serious at advanced nodes. The power integrity gap must be closed in order for Moore’s Law to continue in effect.”
While it’s relatively easy to put in enough decoupling capacitors to deal with a one-off event that stresses the power grid, a strong decap solution also must cope with several consecutive stress cycles. That depletes the local decap so that it’s no longer effective, noted Peter Greenhalgh, an ARM fellow and director of technology in the company’s CPU Group. “At this point the circuit breaks and an incorrect value is propagated. With the latest nodes, and at the frequencies designs are now being implemented, it is a combination of inductive and capacitive effects that are creating the largest challenges.”
Arvind Shanmugvel, director of application engineering at Ansys, agreed. “Voltage drop in ICs has always been a problem for chip designers due to the parasitic RLC of the power delivery network. In advanced technology nodes, this problem has been exacerbated due to the rapid decrease in supply voltage. Cutting-edge SoCs are now designed in 16nm or 7nm technology nodes. The operating voltage for a 7nm process is currently at 500mV. In contrast, the operating voltage for an older 32nm process was 900mV. The threshold voltage for the transistors in both technology nodes however, has not changed much. This, in turn, leads to a much smaller noise margin (Vsupply – Vthreshold) for the 7nm node that designers need to consider during the design process.”
Voltage drop has direct implication on the performance of a chip. If the supply voltage of a device is compromised, it’s switching speed is directly affected. This will lead to a slowdown in the timing paths and can affect the performance of the chip. Voltage drops that exceeds the noise margins for devices also can cause incorrect logic propagation and chip failures. And given that the cost of failures for advanced technology nodes is quite high, one needs to ensure all operating modes are checked for voltage noise issues before sign-off, Shanmugvel said.
Specifically, what’s happening is that with the move down to advanced nodes such as finFET technologies, the operational voltage supply also moves down to sub-volt ranges, such as 0.55v, explained Jerry Zhao, product management director, power signoff at Cadence. “While our power supply is halved, we are still packing more circuitry onto the die. This, in turn, requires a more sophisticated power grid network than ever before. A strong power grid design is important because any variation of the voltage value alone can cause the power grid to drop to a point where the effective voltage supply of a gate (an instance) slows down its performance. This is a timing issue, or it may even cause a malfunction when the voltage drop (IR-Drop) is large. The latter case is obviously a silicon failure due to the voltage drop.”
Another aspect in power integrity is the electromigration (EM) phenomenon, which is the result of strong current (electrons) flowing along the metal wire over a long period of time. The impact of EM is that it can narrow or break a metal wire, creating a reliability issue down the road. To avoid EM violations, care should be taken so that the current doesn’t exceed its limitation based on the characteristics and physical geometry of that metal wire. Such limitations, or EM rules, are well-defined by semiconductor manufacturers. Unfortunately, similar to DRC rules, they have also become very complex from one process node generation to another, especially at finFET nodes because of the 3D transistor architecture and finer geometries, he said.
EM rules should later be carefully coded into chip design tools, such as digital implementation (place and route) and EMIR (electromigration and IR drop) power signoff, and be used as much as possible to guide a designer to a cleaner design. To analyze a design’s power integrity problem, there should be a “total solution” package spanning transistor to gate and chip to system, Zhao said.
“Not only should we have such analysis tools, but we should also have a link between such analysis and design implementation so that we can accelerate design closure,” he said. “From the analysis tool, the place and route tool should understand where the voltage occurs and what has caused it, and then seek a solution. This coherent design process should start as early as the floor-planning stage, during which the power grid can be evaluated for its strength. Another way to fix a large voltage drop violation after place and route is to ‘massage’ a local placement to relocate an ‘aggressor’ cell nearby, which may reduce or even eliminate that voltage drop. On the EM front, a good example is to partially widen a metal wire or size its driver cell to eliminate a signal EM violation.”
Still, one of the biggest advantages of moving to finFETs is ultra-low voltage operation, where devices can function at 0.5V and often even below that, said Mary Ann White and Bernadette Mortell, both product marketing directors in the Design Group at Synopsys. They noted this this immediately provides dynamic power savings, but can introduce new timing challenges due to variation and waveform distortion effects. “There is a lot more variation with the smaller finFET process geometries, especially at 10nm and below, due to the shrinking node process and wire alignment of the various lithographic effects. At ultra-low voltages, the variation is more magnified, where waveform distortion also happens due to increased wire resistance and Miller effects (higher capacitance).”
It also should be noted that the voltage drop problem is not isolated to the chip alone, Ansys’ Shanmugvel asserted. “We see more and more issues related to voltage noise across the package and board, as well. Improper decap schemes or impedance mismatch on the package or board can cause global voltage noise issues at the lower frequency spectrum. Advanced 3D packaging schemes such as (TSMC’s) InFO-WLP (Fan-Out Wafer Level Packaging) add yet another dimension to the simulation complexity. All the different wafers in the package, along with the RDL and micro-bumps, need to be modeled for proper voltage noise simulations. These designs also require high capacity solvers with distributed or elastic architectures to address their simulation needs.”
Further, design complexity for advanced nodes also has increased tremendously. As more functionality gets integrated on the same SoC, designers need to simulate multiple operating modes along with several PVT corners. These scenarios need to be analyzed for voltage drop to ensure proper operation across all modes.
Designers typically have a certain margin for voltage drop they should meet across these scenarios. Arriving at the proper switching scenarios is not an easy task during the design process. The scenario should be logically consistent and show localized switching events and global switching events to stress the on-chip and package/board power delivery network. Ensuring this scenario coverage is critical for voltage drop sign-off for these advanced technology nodes, Shanmugvel said.
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