FD-SOI Strains For The Future

The search is on for a way to improve performance.

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One of the challenges facing supporters of FD-SOI is the need to provide a pathway to improved performance. While FD-SOI wafers offer some significant advantages over bulk silicon wafers, performance enhancements like strain and alternative channel materials are more difficult to implement in the thin SOI environment. On the other hand, once a fab is willing to incorporate layer transfer techniques at all, those techniques can support a wide range of alternative wafer structures.

In a paper presented at this year’s VLSI Technology Symposium, A. Bonnevialle and colleagues at CEA-LETI discussed the integration of strain boosters with FD-SOI CMOS. In previous work, wafer-level tensile strain has given nFETs as much as a 20% ON-current boost, but has been detrimental to pFET devices on the same wafer. Similarly, wafer-level compressive strain degrades nFET performance. How then, to achieve localized strain effects?

One CEA-LETI approach starts with a thin SOI wafer and prepares compressed SiGe channels (for pMOS) and trench isolation by standard methods. Then, to apply tensile strain to the nFET regions, the group covered the pFET regions with a protective SiN layer and selectively grew SiGe on the nFET regions. The SiGe served as a template for recrystallization of the silicon under tensile stress, then was removed. This so-called “STRASS” approach (strained silicon by top recrystallization of amorphized SiGe on SOI) allows for further mobility enhancement by increasing the germanium content of the SiGe layer.

SiGe pFETs grown on thin SOI already have a degree of compressive strain. To increase performance further, the CEA-LETI group took advantage of the SiN-lined trenches already used in the shallow trench isolation process. Capping the pFET regions with tensile SiN and annealing before deposition of the trench oxide imposed additional compression on the SiGe channels.

Together, the researchers said, they were able to achieve localized tensile (nFETs) and compressive (pFETs) strains on a single wafer, allowing the extension of FD-SOI technology to sub-14nm process nodes.

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