It costs nearly three times more to design a finFET-based chip than a 28nm planar chip, and it takes more than twice as long to get working silicon.
The foundry business is heating up as some new and large players are entering the 16nm/14nm finFET market. But foundry customers are taking longer than expected to migrate to finFETs amid some technical and cost issues.
On the foundry front, Intel Corp. has been the sole player in finFETs for some time. But now, Samsung and TSMC are entering the hotly contested 16nm/14nm finFET foundry business. And GlobalFoundries will enter the fray later this year.
In general, though, the foundries were originally projected to move into volume production for 16nm/14nm finFETs by the third quarter of 2014, according to Gartner. “Compared to the schedule we know today, it seems that all suppliers have experienced two to four quarters of delays in 16nm/14nm finFETs,” said Samuel Wang, an analyst with Gartner.
As it turns out, finFETs are harder to master than previously expected. For some time, the foundries have been wrestling with new multi-patterning flows and nagging yield issues with finFETs. And the various and different backend interconnect schemes from the foundries have created some confusion in the market.
Case in point: Intel moved into 14nm finFET production late last year, which was six or so months later than expected. Intel blamed the delay on yield issues. As a result, Intel’s big foundry customer, Altera, has pushed out the production date of its 14nm-based FPGAs from 2014 to late 2015.
More recently, Intel and the other foundries have solved some, if not all, of the manufacturing issues with finFETs. But the delays have pushed out the production schedules of other foundry customers in the finFET arena. Still others, namely Apple and HiSilicon, hope to ramp up finFET-based chips in 2015, but these are the exceptions to the rule. “16nm/14nm should be a high-volume node in 2016,” Wang said.
It’s not just the foundries that are causing the delays, though. Chipmakers have had to change their design methodologies to account for double patterning at 16nm/14nm. At 20nm, much of the coloring of different mask layers was hidden from design teams. That’s no longer true at 16nm/14nm, and it has forced them to make changes in a flow that until these new nodes was a masterful piece of clockwork.
“In the past, you could leave DRC until you were done with the base layer tapeout,” said Sudhakar Jilla, group director for marketing for place and route at Mentor Graphics. “That normally took two weeks. But you can’t leave two weeks to finish DRC and coloring. It’s not possible.”
Process variation has added more delays. The number of corners that need to be addressed has increased, which impacts the schedule for timing closure. There is simply more stuff to consider—four corners is now more like 20 corners, and instead of pin access for one cell there might be five pins per cell, Jilla said. On top of that, design teams must now contend with dynamic power density, which wasn’t an issue at previous nodes. Until now, the big concern has been leakage current. These are not simple subjects to master, even for experienced design teams.
There are other factors at play here, as well. Some customers are sticking with their foundry partners for finFETs, while others are switching camps. Some are dabbling with 16nm/14nm finFETs, but they are waiting for 10nm finFETs. It may take a scorecard to keep track of the changes before the dust settles.
Foundry customers with deep pockets can afford to make the migration to finFETs, but it will cost more money—up to three times what it costs to design and develop a 28nm planar device. Many other foundry customers can’t afford these costs and will be forced to stay at the 28nm node and above—at least for now. This isn’t all bad news, because there is a sizable IC market that does not require finFETs.
Moreover, with Samsung and TSMC in the finFET mix, foundry customers have some new and competitive options. But most, if not all, foundry customers are still in the same boat and are asking the same question: What are the challenges with finFETs?
At the 20nm planar node, the control of the gate becomes problematic in chip designs. Chips, in turn, are running into the so-called short-channel effects.
So at 20nm, chipmakers must migrate from conventional planar processes to finFET transistors at 16nm/14nm and beyond. “The finFET provides much lower power,” said Kelvin Low, senior director of foundry marketing for Samsung. “The channel, where the current flows, is 3D. We had to make it 3D so that the amount of current flowing in the area increases.”
But moving from planar to finFETs is easier said than done. “What has changed is the complexity of product design and technology development,” said Mark Liu, president and co-chief executive of TSMC, at a recent event. “IC design and systems software complexity have demanded the preparation of our design platform much earlier than before. Typically, (it’s) one year earlier than before. As a consequence, new product design requires much larger resources, which translates into higher design costs.”
All told, there are three basic challenges in moving to finFETs—design, manufacturing and cost. On the design front, the big change for foundry customers is the move from a single patterning flow at 28nm and above to a Double Patterning scheme at 20nm and 14nm.
“Designers have been very familiar with planar technology architectures for many generations,” Samsung’s Low said. “For designers, it’s a learning process (with double patterning). In double patterning, we have two masks. You have color A and color B. Designers need to understand how to deal with two colors now, which they have never experienced in the past.”
IC designers will encounter other issues as well. “Even though finFETs get the most publicity, double patterning makes the design flow a little bit more complex,” said Richard Trihy, director of design methodology at GlobalFoundries. “This impacts the entire design flow, such as parasitic extraction and variation. It impacts the implementation tools for place and route. Of course, it impacts DRC, which becomes a more complicated step.”
In response, the foundries and the EDA community are providing new EDA tools and flows to help enable the migration to finFETs. The tools make the migration as transparent as possible for designers, Trihy said.
Chipmakers also face challenges on the manufacturing front. The hard part is to make fins with consistent heights during the etch process. Imprecise fin patterning could cause variations. In addition, finFETs have an assortment of three-dimensional structures that are difficult to measure. Finding killer defects is also problematic.
But perhaps the biggest issue is cost. The average IC design cost for a 28nm device is about $30 million, according to Gartner. In comparison, the IC design cost for a mid-range 14nm SoC is about $80 million. “Add an extra 60% (to that cost) if embedded software development and mask costs are included,” Gartner’s Wang said. “A high-end SoC can be double this amount, and a low-end SoC with re-used IP can be half of the amount.”
On top of that, it takes 100 engineer-years to bring out a 28nm chip design. “Therefore, a team of 50 engineers will need two years to complete the chip design to tape-out. Then, add 9 to 12 months more for prototype manufacturing, testing and qualification before production starts. That is if the first silicon works,” he said. “For a 14nm mid-range SoC, it takes 200 man-years. A team of 50 engineers will need four years of chip design time, plus add nine to 12 months for production.”
If that’s not enough, there is also a sizable jump in manufacturing costs. In a typical 11-metal level process, there are 52 mask steps at 28nm. With an 80% fab utilization rate at 28nm, the loaded manufacturing cost is about $3,500 per 300mm wafer, according to Gartner.
At 1.3 days per lithography layer, the cycle time for a 28nm chip is about 68 days. “Add one week minimum for package testing,” Wang said. “So, the total is two-and-half months from wafer start to chip delivery.”
At 16nm/14nm, there are 66 mask steps. With an 80% fab utilization rate at 16nm/14nm, the loaded cost is about $4,800 per 300mm wafer, according to Gartner. “It takes three months from wafer start to chip delivery,” he added.
Who’s on first?
At 14nm, wafer costs also are going up due to double patterning. Intel, for one, attacked the problem on two fronts. First, it over-scaled the transistor density. Second, it scaled the interconnect pitch by 0.65x, from 80nm at the 22nm node to 52nm at the 14nm node.
In contrast, other foundries combined a 16nm/14nm finFET transistor with a 20nm planar backend. “If you take a look at what others are doing, they chose not to scale the area, which just kills their cost,” said Yan Borodovsky, a senior fellow and director of advanced lithography at Intel.
At 22nm, Intel’s finFET technology has a fin pitch of 60nm and a fin height of 34nm. At 14nm, the fin pitch and height are both 42nm. Intel also went to thinner and taller fins, which are rectangular in shape. “That improves the electrostatics of the fins,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel.
At one time, Intel had a two- to three-year lead in finFETs. But the company’s delays at 14nm are giving its foundry rivals time to close the gap.
Last year, though, TSMC disclosed it would experience share losses in finFETs in 2015. TSMC decided to focus on 20nm in 2015 and finFETs in 2016. In contrast, Samsung basically skipped 20nm to focus on finFETs in 2015, thereby getting the upper hand in the market.
In fact, Samsung entered the finFET market in February by rolling out a chip based on the process. The chip, dubbed the Exynos 7420, is a 64-bit, eight-core SoC. It is based on an 11-metal level process and includes a high-k/metal-gate technology, according to TechInsights. The gate length is about 30nm, with a 77nm contacted gate pitch, according to the firm.
As part of the chip introduction, Samsung also entered the 16nm/14nm finFET foundry market. “We have declared that 14nm is in mass production,” Samsung’s Low said. “We are now seeing a change. What is apparent is there is now a true choice for customers of finFETs.”
Samsung is also ramping up its capacity for foundry customers. In fact, for the next iPhone, Apple has selected Samsung over TSMC for a large percentage of its chips based on 14nm finFETs, according to Pacific Crest Securities.
Today, Samsung has roughly 11,000 wafer starts per month (wspm) of 14nm capacity, which represents about 10% of its total 300mm fab capacity, according to Pacific Crest Securities. Over time, Samsung is expected to convert some of its 28nm capacity, giving it a total of 46,000 wspm of 14nm capacity, according to the firm.
Another foundry vendor, GlobalFoundries, licensed Samsung’s 14nm finFET process some time ago. In its New York fab, GlobalFoudries is capable of ramping up around 30,000 wspm of 14nm finFET capacity, according to Pacific Crest Securities. Later this year, GlobalFoundries will move into finFET production.
Not to be outdone, TSMC will begin volume production for its 16nm finFET process by the middle of this year. By the end of 2016, the company plans to have an installed capacity of 100,000 wspm for 16nm finFET technology, according to J.K. Wang, vice president of 300mm fab operations at TSMC.
TSMC is positioning itself in hopes of regaining share in finFETs. In fact, it’s too early to declare a winner in the finFET foundry business. In many ways, the race has just begun.
— Ed Sperling contributed to this story.