Improving power network integrity and reducing voltage drop during design implementation.
As the industry moves to ever more advanced technology nodes, managing power has emerged as a primary challenge in modern SoC design. With smaller nodes, the wires become taller and narrower, which increases the resistivity and leads to more pronounced voltage drop effects. Electro-migration effects are also more severe at advanced nodes, causing serious reliability concerns. Both RTL synthesis and P&R tools must correctly interpret the power intent and then implement a reliable power network.
Planning the power budget for your design starts at the architectural level, but it is also important to deploy low-power design techniques through the digital implementation flow.
Power-aware RTL synthesis
Every SoC has a power budget that’s driven by factors such as power supply, battery life, heat constraints, and performance. In order for the designer to meet the design power budgets, it is essential to consider power as part of the cost function early in the design flow. Controlling power and keeping power density in check will automatically help minimize IR drop issues in the design.
Power-aware RTL synthesis will optimize dynamic and leakage power so that the generated gate-level netlist is ready for backend implementation. RTL synthsis should include advanced clock gating, multi-Vt, and multi-VDD aware synthesis. With newer synthesis technologies that are capable of physically aware power analysis, designers can get early feedback on the power consumption, which lets them detect and fix problems early and design the power grid more efficiently.
Reducing voltage drop with a quality power grid
Minimizing voltage drop has long been a standard task during the physical design stage. Voltage drop is caused by the resistance of power/ground wires used to distribute power on the chip. Because it is directly proportional to the power density, the largest voltage drops usually occur in areas that have high power/current density. There is a circular dependency between power consumption, voltage drop, and performance—more power consumption leads to more voltage drop (and higher temperature), which in turn leads to performance degradation. From an analysis standpoint, designers need to look at both static voltage drop and dynamic voltage drop and fix any issues to ensure that the power grid is robust and the design functional.
The power grid must supply all the power/ground connections for on-chip components and also power pads to supply power to the chip, power rings and power rails. The power grid is created during floor-planning based on power budget estimates, then refined to deal with voltage drop problems or other power hotspots. Voltage drop though the power/ground network can be analyzed during the floor-planning stage to provide early feedback for power grid design. Detecting excessive voltage drop requires early and accurate power analysis to guide resizing the wires, create or remove rails, or add power rings around macros.
To fix voltage drop issues, the designer typically increases the width of the power grid or adds additional straps to minimize resistance. Of course, these changes can potentially use up tracks that would be use for signals, which could lead to congestion, high utilization, and timing problems. Designers must carefully balance these conflicting requirements to achieve the best power network without degrading any of the other design metrics.
Preventing electromigration to improve circuit reliability
Electromigration is a phenomenon that causes the metal ions in the wires to migrate due to the current flow. Electromigration occurs when the current density in the wires exceed the specified limits for a given process. Migration of the ions eventually causes either opens or shorts in the wires, resulting in long-term reliability issues. Electromigration in power and ground rails also causes timing problems, because the increased track resistance associated with an open can result in a higher voltage drop. This, in turn, will cause increased delays and noise susceptibility in the affected logic gates. Analysis during physical design can find potential electromigration issues and fix the problems by either widening the wires or adding additional power straps to meet the current density targets. Considering current density as a cost function along with the other design metrics helps significantly improve the reliability of the design.
Today’s low-power designs require advanced power reduction techniques during both RTL synthesis and physical implementation. Power optimization needs to start at the architectural level and then be carried forward throughout the design flow to ensure optimal power density distribution in the design. Another key requirement for a true low-power design environment is early analysis capabilities for power and voltage drop to identify and resolve problems early.
Figure 1. Analyzing power during RTL synthesis lets designers identify and fix issues early in the flow. This snapshot from Mentor’s RealTime Designer shows power density hotspots highlighted during the RTL floorplanning stage.