Reaching The Power Budget

Why power is still a problem, how it will get worse, and what can be done about it.

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Everything related to power in chip design today is a big deal—and it’s just getting bigger.

Meeting the power budget is becoming harder at each new node, but it’s also becoming difficult in a number of new application areas at existing nodes. That’s a big problem because power is now considered a competitive advantage in many markets. It’s also one of the most technically difficult aspects of design to bring under control and to maintain throughout the design flow.

“Traditional back-end and implementation-focused techniques can no longer achieve the kind of power savings often needed for power-critical markets,” said Saurabh Kumar Shrimal, senior low-power technologist at Mentor Graphics.

Unlike in the past, having a good specification is no longer enough. Designs, and IP used in those designs, still need to be qualified for power, but that’s just the starting point. All of this has to be delivered in the context of brand new features, more connectivity, in a package and price point that appeals to a specific market segment. And it has to be done within a tightening market window and with some consistency in the measurements.

“Projects need to know this very early on in the design phase, and currently there are no good metrics to qualify it,” said Shrimal. “It is important to have these power qualification metrics for designs and IP so that overall power budgets can be achieved in a predictable amount of time, and so companies that are competing on power can decide early on how to do it.”

Today it is common to measure or qualify the quality of IP using various structural and functional coverage metrics. But Shrimal said that to tackle power challenges, tool offerings should include a way to qualify the design for power. That needs to include absolute power consumption, which is done today, as well as power redundancy or wasted power in the design.

“Ideally, this (wasted power) number should be zero,” he said. “This kind of metric and qualification will both help the designer’s productivity, by pointing them that where and how to fix the problem, and to know whether the design has the ability to ever meet the budget. It can no longer be just a game of traditional clock gating to save power. RTL designers will need to change multiple aspects of the design — register, combinational, clock tree, memory — to resolve the power problems. Only with this approach will they know early enough in the design cycle where they stand in achieving their power budget and deliver the project on time and on budget.”

This reaches well beyond where most chipmakers and IP vendors are today.

“Just reaching the power budgets is still a challenge,” said Rod Metcalfe, product management group director at Cadence. “With all the mobile devices in the world today, power is dominant in terms of the specification of a typical device, and it’s getting more and more aggressive. People are getting better and better at low-power design, but there are always more challenges. And they always feel like they can improve. The tools have certainly improved massively to consider power, and the results we get today are so much superior to a few years ago. But can we go further? Yes. And users are actively moving in that direction.”

All of the major EDA and IP vendors are well aware of the issues. So are chipmakers in the mobile space, where battery life remains a big issue. Chipmakers in other markets are slowly coming around.

“We continue to push performance aggressively, but power densities remain troublesome, and it is as imperative as ever that we have a handle on power (and thermal) management within our platforms,” said Alan Gibbons, power architect at Synopsys.

As such, the more visibility provided to both hardware and software designers early in the design flow as far as power behavior of their platforms, the greater the opportunity for them to meet these aggressive power budgets, he explained. “Attempting to correct a power budget miss late in the design flow is near-on impossible, and the only approach that has any chance of success is to design-in energy efficiency from the start.”

Training required
Engineering teams are getting it more right than in the past, but everyone agrees there is still a lot of room for improvement.

“Industries like networking, which have traditionally focused on performance and functionality, have not adopted power methodologies,” said Preeti Gupta, director of RTL product management at Ansys. “It’s not that there aren’t power methodologies today where they can define power budgets and try to achieve them through the various low-power techniques available, but power is not as big of a deal for them even now. It is still very secondary or tertiary.”

In areas like mobile and IoT, it’s a different story. Case in point: Intel this month issued a full recall for the Basis Peak Fitness watches, which can cause skin burns.

“This is not even a networking device, said Gupta. “It is a handheld device, and they suspect the part that is monitoring the heartbeat continuously is burning up and causing skin burns in 0.2% of these devices. But that is still a huge number.”

This begs the question of just how the design team considered power and thermal for this device.

“The budget is very well known,” she said. “It is 3 watts for handheld devices. We know that. This is a prime example of how power budgeting is getting worse with the addition of so many complex techniques that each talk to each other. We are adding so many complex modes of operation. How many combinations can you really simulate?”

Scaling with power
To complicate matters, most chips have more transistors than previous generations. While scaling is getting harder, particularly at the most advanced nodes, not everyone is at those nodes. And those companies that are expect to continue scaling for at least one or two more nodes.

“With Dennard scaling, which we had to fall off of, you doubled the number of transistors, but the average distance between transistors got shorter, and therefore the capacitance would go down,” said Drew Wingard, CTO of Sonics. “You would change the supply voltage, and all of these things were supposed to go in so that it didn’t cost you more energy to do the increased amount of work. What broke was the capacitance of the wires stopped scaling down linearly with the width of the wires, because the contribution of the capacitance of the wire from the sides became much more than the parallel plate capacitance. So the capacitance aspect of scaling stopped helping.”

That was compounded by the inability to continue scaling down the voltage.

“They tried to scale that, but then leakage started becoming a big problem,” Wingard said. “So we lost in three different ways. We couldn’t scale the voltage. When we did scale the voltage, leakage became a huge problem. And we couldn’t scale the capacitance in the way it was supposed to. For all of these reasons, it means that to integrate more functions and use that functionality, the power to get it done goes up.”

Getting more aggressive
With physics as the big limiter on scaling, the only option left is to get far more aggressive in managing energy. But that also can be problematic because it requires more design time to reduce the amount of power usage, and most chipmakers say that time to market is currently their top concern.

At least part of that can be dealt with from a methodology standpoint. “Consider—and include—power early in the design flow, and do not lose sight of it at any point,” said Synopsys’ Gibbons. “With flexibility in power modeling, and associated EDA tooling, an efficient power-aware system design solution is being provided to design teams to alleviate power budget challenges.”

There are new avenues being explored to provide more standardized approaches to power, as well. This isn’t easy, because power scenarios are unique to each design and use case.

Wingard noted that the basic setup techniques that can be used to minimize the amount of energy and/or power are well understood, so it isn’t the case that there’s any fundamental lack of understanding of the techniques. “The question is, which ones to apply, where to apply them, how often to apply them, and maybe most importantly, when in the process of doing the design do you decide you’re going to apply them?”

And this is where the interesting part of the challenge lies. “We’re trying to push the problem as hard as the physics allow, but we recognize that depending upon where you are coming from — the characteristics of the application, the things you’ve done in the past— that you may not believe today that you need to be this aggressive. Or, you may not feel comfortable doing this kind of work. That’s why how this plugs into the rest of the design process, the design flow, backend tools, is so important.”

Sonics has been focused on adding more granularity into power management to limit the power wasted during idle moments of active power. Others are working on adding more granularity into power domains, combining that with such techniques as near-threshold performance, forward and reverse body biasing (at 40nm and above using bulk CMOS, and at 28nm and 22nm using FD-SOI), as well as shutting down blocks or portions of blocks when they are not needed.

Ansys’ Gupta has seen an increase in the use of system-level vectors, as well. “This is running the device in its real application. In the early part of my career, what I observed is people would use any functional vector that they had handy, and use that to look at power—without consideration of whether it was the dominant mode of operation for the device, or if it was a mode that causes a lot of peak power consumption. So you want to bring down that peak power consumption. All the time, I’ve seen that in power methodologies. It’s the verification teams that have grown larger. These are the teams that are creating power vectors. Now, people are looking at system-level vectors like an OS boot-up sequence, which could be one second. The industry is evolving based on such things as human injuries, and trying to catch them as early as you can and design for it.

Synopsys, meanwhile, is leveraging UPF 3.0 IP power models, which can be created at the outset. “We operate with highly abstract power data early on during system-level design, and then continually refine that power information as the design (hardware and software) continues to be refined,” Gibbons said.

These are just a few examples of the new thinking on power budgets: how to model it, maintain it, and verify it. With new tools and techniques still under development, it will be interesting to see which approaches take hold with the engineering community.

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