In-Design Rail Analysis Is A Beautiful Thing

As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ultimately create silicon that could end up in your smartwatch, your electric vehicle, or the latest cell phone – how amazing! Consumers concerns include product reliability and robustness, which bri... » read more

Deep Learning Market Forces

Last week, eSilicon participated in a deep learning event at the Computer History Museum – “ASICs Unlock Deep Learning Innovation.” Along with Samsung, Amkor Technology and Northwest Logic, we explored how our respective companies form an ecosystem to develop deep learning chips for the next generation of applications. We also had a keynote presentation on deep learning from Ty Garibay, C... » read more

Xceler Systems: Graph Architecture

An inventor who made foundational contributions to three key ways we move data through complex systems is developing a new type of neuromorphic chip to accelerate AI applications. Rather than try to build a computer that looks like a brain, Gautam Kavipurapu and Xceler Systems are building smaller bits that act like synapses. When the design is advanced enough and there are enough of them, t... » read more

Counting On Cryptocurrency

While cryptocurrencies may still be in the infancy of market development and adoption, the semiconductor industry has certainly felt the potential of blockchain technologies. In its fourth quarter 2017 earnings conference, TSMC commented on the strong demand from cryptocurrency-related businesses since the second half of 2017. These “mining” markets are driving leading-edge business at TSMC... » read more

Is Advanced Packaging The Next SoC?

Device scaling appears to be possible down to 1.2nm, and maybe even beyond that. What isn't obvious is when scaling will reach that node, how many companies will actually use it, or even what chips will look like when foundries actually start turning out these devices using multi-patterning with high-NA EUV and dielectrics with single-digit numbers of atoms. There are two big changes playing... » read more

eSilicon Builds ASIC Business On Leading-Edge Chip Design

This paper explores how advanced application specific integrated circuits (ASIC) chip design and manufacturing for leading-edge applications such as networking and artificial intelligence can be successfully outsourced. The company we profile is eSilicon, which has capabilities in 2.5D packaging, high-bandwidth memories (HBM), and silicon IP for fast memories and SerDes designs. The company ha... » read more

Tech Talk: Debugging ASICs With Embedded FPGAs

Valy Ossman, senior architecture and applications engineer at Flex Logix, discusses the advantages of debugging an ASIC using an embedded FPGA, including time to market, flexibility in design, and after-market changes. » read more

What’s Next With Computing?

At the recent IEDM conference, Jeff Welser, vice president and lab director at IBM Research Almaden, sat down to discuss artificial intelligence, machine learning, quantum computing and supercomputing with Semiconductor Engineering. Here are excerpts of that conversation. SE: Where is high-end computing going? Welser: We are seeing lots of different systems start to come up. First of all,... » read more

Tech Talk: eFPGA Programming

Kent Orthner, system architect at Achronix, explains how to program an embedded FPGA and what's different for ASIC engineers. » read more

Evaluating Speedcore IP For Your ASIC

By exploiting Achronix Speedcore embedded FPGA (eFPGA) IP — IP proven in multiple ASIC designs for wireless, datacenter and high-performance computing (HPC) applications — designers of SoCs can now add logic programmability to their solution, resulting in a single ASIC that can adapt to many applications. While many system architects may already have strong ideas on how an eFPGA core could ... » read more

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