Tech Talk: eFPGA Test


Volkan Oktem, director of product applications at Achronix, explains how to design a test approach for embedded FPGAs, including how to plan for sufficient coverage and how much it will cost. https://youtu.be/aGXd8QH-BfY   Related Stories Tech Talk: EFPGA Acceleration When and why to use embedded FPGAs. » read more

Portable Stimulus Status Report


The first release of the Portable Stimulus (PS) standard is slated for early next year. If it lives up to its promise, it could be the first new language and abstraction for verification in two decades. [getentity id="22028" e_name="Accellera"] uncorked the PS Early Adopter release at the Design Automation Conference (DAC) in June. The standard has been more than two years in the making by t... » read more

When Is Verification Complete?


Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This trend has been underway for the past couple of process nodes, but it takes time to spot trends and determine whether they are real or just aberrations. The Wilson Research Group conducts a ... » read more

Verification Unification


Semiconductor Engineering brought together industry luminaries to initiate the discussion about the role that formal technologies will play with Portable Stimulus and how it may help to bring the two execution technologies closer together. Participating in this roundtable are Joe Hupcey, verification product technologist for [getentity id="22017" e_name="Mentor, a Siemens Business"]; Tom Fitzpa... » read more

Safety Plus Security: A New Challenge


Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Verification Unification


There is a lot of excitement about the emerging [getentity id="22028" e_name="Accellera"] [getentity id="22863" e_name="Portable Stimulus”] (PS) standard. Most of the conversation has been about its role in [getkc id="11" kc_name="simulation"] and [getkc id="30" kc_name="emulation"] contexts, and in the need to bring portability and composability into the verification flow. Those alone are st... » read more

Whatever Happened to High-Level Synthesis?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high lev... » read more

Rediscovering Coverage Insurance


When coverage comes up in conversation, if it comes up at all, it’s always a matter of car, home or health insurance. Coverage and functional verification are unlikely to be used in that discussion, or any other for that matter. That’s too bad because engineering groups grapple with when is enough verification enough, like some kind of coverage insurance. Oh sure, simulation and emulatio... » read more

Fault Simulation Reborn


Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the quality of manufacturing test vectors. That task was replaced almost entirely by [getkc id="173" comment="scan test"] and automatic test pattern generation (ATPG). Today, functional safety is cau... » read more

Confidence In 7nm Designs Requires Multi-Variable, Multi-Scenario Analysis


As designs move toward 7-nanometer (nm) process nodes, engineering and production cost dramatically increases and the stake in getting the design right the first time becomes significantly higher than ever before. You are faced with the question, “how confident are you in your design analysis coverage?” Tighter noise margin, increasing power density, faster switching current and greater ... » read more

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