#54DAC: A New Beginning

I’ve been attending DAC as an exhibitor since 1992, and serving on the executive committee since 2012. I am thrilled to serve as General Chair for the 54th iteration of this grand conference. (And no it’s not too early to think about DAC. The call for contributions is open now.) Through the years I have seen some big industry changes, most driven by the increasingly powerful tools and autom... » read more

The Week In Review: Design

Numbers EDA and IP sales increased 5.6% in Q2 to $2.013 billion, up from $1.907 billion in the same period in 2015, according to the most recent Electronic System Design Alliance numbers. Asia/Pacific revenue increased 10.9% to $608.1 million; Japan increased 15.7% to $211.4 million. The Americas increased 4.4% to $908.4 million. IP Cadence launched the latest generation of its Xtensa ... » read more

What’s Next For UVM?

The infrastructure for much of the chip verification being done today is looking dated and limited in scope. Design has migrated to new methodologies, standards and tools that are being introduced to deal with heterogeneous integration, more customization, and increased complexity. Verification methodologies started appearing soon after the release of SystemVerilog. Initially they were inten... » read more

No More Easy IP Money

The semiconductor intellectual property ([getkc id="43" kc_name="IP"]) industry is two decades old, but questions are still being asked about what's wrong with it and what needs to be fixed. Normally these kinds of issues are reserved for fast-moving, young industries, not one that is the backbone of semiconductors. Design reuse has become an indispensable part of the design of nearly all el... » read more

Balancing Emulation And FPGA-Based Prototyping For Software Development

This year’s Design Automation Conference (DAC) has just finished and confirmed some of the trends I discussed in my last blog, “The Top Five Trends in Verification to Watch For at DAC 2016”, specifically when it comes to the set of connected engines, or “COVE” as Jim Hogan dubbed it. The Cadence Theater at DAC is always a good opportunity to listen to hands-on customer experiences, an... » read more

The Week In Review: Design

Tools & IP Synopsys uncorked PHY and Controller IP for PCI Express 4.0 architecture, which the company says reduces latency by up to 20% and area by 15% compared to the previous implementation. The IP supports lane margining to assess performance variation tolerance. PLDA announced a PCIe 4.0 development platform, and provides a PCIe 3.0-x8 (upstream) to PCIe 4.0-x4 (downstream) Integ... » read more

Why IP Subsystems And Why Now?

At the recently concluded DAC 2016 conference in Austin, Texas, I had the opportunity to participate in a tutorial on IP Subsystems on Wednesday the 8th. Also participating were Marco Brambilla, Director of Engineering at Synapse Design and Drew Wingard, CTO at Sonics. The reality today is that device complexity in many applications has risen to levels that require increasing amounts of disc... » read more

Decoding The Brain

At the Design Automation Conference this year, Lou Scheffer, principal scientist for the Howard Hughes Medical Institute, gave a visionary talk entitled Learning from Life: Biologically Inspired Electronic Design. Scheffer is an IC design guy who came through Stanford and Caltech and worked for HP and [getentity id="22032" e_name="Cadence"] before switching to the medical field eight years a... » read more

The Week In Review: IoT

Design Automation Conference ARM Holdings announced that its DesignStart initiative to enable easy creation of chip designs using ARM Cortex-M0 intellectual property now takes in electronic design automation tools and design environments offered by Cadence Design Systems and Mentor Graphics. “Simplifying access to EDA tools from Cadence and Mentor Graphics will further spur rapid innovation,... » read more

DAC Day Four: Excitement And Risk

One thing that was new to DAC this year, was an art exhibit. These were pieces of artwork related to our industry, such as chip plots, or more abstract ideas based on design data or analyses. They received many more entrants than their wildest dreams and had to choose a winner from over 80 pieces, but the grand prize was won by a 3D model of a finFET by David Freid of Coventor. This piece was ... » read more

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