SerDes Signal Integrity Challenges At 28Gbps And Beyond


After nearly fifty years, NRZ technology continues to pose significant challenges as data rates approach 56Gbps and refreshed standards mandate increased receiver sensitivity (down to 35 mV). With shorter unit intervals and closing eyes, triggering becomes ever more complex and requires enhanced receiver equalization such as continuous-time-linear equalization and decision feedback equalization... » read more

Debug Is About To Get Really Interesting Again


One of the great unheralded chapters in the history of electronics design is debug. After all, where there have been designs, there have been bugs. And there was debug, engaged in an epic wrestling match with faults, bugs and errors to determine which would prevail. Think about system in the 1970s and '80s. A typical system would consist of a CPU, (EP)ROM, RAM, Peripherals (PIC, UART, DMA, T... » read more

Finding The Unexpected In High Performance Designs


It was growing dark as I drove a winding road on Mt. Hood, deep in the American northwest forest. The firs were thick, creating a lot of shadows and making it tough to see things clearly. Then out of the corner of my eye, I swear I saw a 10-foot “man” covered with brown fur. It looked a lot like a Wookie. But everyone knows Wookies aren’t real. It had to be Bigfoot! I slammed on th... » read more

Finding Evasive System-Level Bugs Using Memory Consistency Algorithm


Over Easter weekend in 2015 there was a jewelry heist at the safe deposit building at Hatton Gardens in London. The safe deposit vault was in the basement of a building and is used by jewelers in the area for storing large amounts of diamonds, jewelry, precious metals, and cash. The thieves made off with over $300 million in loot, making it the biggest heist in British history. For a while it l... » read more

Tools For Heterogeneous System Development


System architects look to both heterogeneous and homogeneous computing when there are no other options available, but the current thinking is that a system-level software methodology could simplify the design, ease integration of various blocks, and potentially improve performance for less power. While the theory appears sound enough, implementing it has turned out to be harder than expected. ... » read more

Formal’s Roadmap


Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Formal’s Roadmap


Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Choosing Verification Engines


Emulation, simulation, FPGA prototyping and formal verification have very specific uses on paper, but the lines are becoming less clear as complexity goes up, more third-party IP is included, and the number of use cases and interactions of connected devices explodes. Ironically, the lines are blurring not for the most complex SoCs, such as those used in smart phones. The bigger challenge app... » read more

The Trust Burning Debug Cycle From Hell


As bad as The Trust Burning Debug Cycle From Hell sounds, it’s worse than you think. Most of us don’t realize it exists. In my first 10 years as a hardware developer I wrote code like it could never exist! But then came the realization. It’s a cycle that preys on us all. It tempts me constantly. Most of us in hardware development are used to seeing bugs as annoyances at a minimum, thou... » read more

Hypervisors: Help Or Hindrance?


Hypervisors are seeing an increased level of adoption, but do they help or hinder the development and verification process? The answer may depend on your perspective. In the hardware world, system-level integration is rapidly becoming a roadblock in the development process. While each of the pieces may be known to work separately, as soon as they are put together, the interactions between th... » read more

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