Optimizing Your DRC Debug Can Reap Big Productivity Gains


Debugging design violations found by design rule checking (DRC) has always taken a significant share of the time needed to get a design to tapeout. And debug time only increases as the number and complexity of DRC expands with each new process node. Any steps you can take to make your DRC debug process more efficient directly improves your productivity. One technique for minimizing debug tim... » read more

Digital Twins: Making The Vision Achievable


Few business concepts are generating the buzz of digital twins — product replicas that can help target performance issues and allow for true predictive maintenance. While the benefits are obvious, companies have struggled with how to achieve this vision. But now there is a practical solution. To read more, click here. » read more

Finding And Fixing ML’s Flaws


OneSpin CEO Raik Brinkmann sat down with Semiconductor Engineering to discuss how to make machine learning more robust, predictable and consistent, and new ways to identify and fix problems that may crop up as these systems are deployed. What follows are excerpts of that conversation. SE: How do we make sure devices developed with machine learning behave as they're supposed to, and how do we... » read more

EDA In The Cloud


Semiconductor Engineering sat down to discuss the migration of EDA tools into the Cloud with Arvind Vel, director of product management at ANSYS; Michal Siwinski, vice president of product management at Cadence; Richard Paw, product marketing manager at DellEMC, Gordon Allan, product manager at Mentor, a Siemens Business; Doug Letcher, president and CEO of Metrics, Tom Anderson, technical marke... » read more

Tech Talk: Improving Verification


Frank Schirrmeister, senior group director for product management and marketing at Cadence, discusses how to verify different use cases, focusing on software, low-power designs, connectivity, and a variety of end markets. https://youtu.be/gK-0vmIWxJs » read more

Tail End Latency And Server Debug


The rise of the heterogeneous multicore processor has enabled a massive increase in the ability of data centers to deliver advanced services to billions of users worldwide. But the complexity that is now possible has made the optimization of these services difficult to achieve. Providers of heterogeneous multicore SoCs have an opportunity to deliver the tools to make optimization of highly dist... » read more

When AI Goes Awry


The race is on to develop intelligent systems that can drive cars, diagnose and treat complex medical conditions, and even train other machines. The problem is that no one is quite sure how to diagnose latent or less-obvious flaws in these systems—or better yet, to prevent them from occurring in the first place. While machines can do some things very well, it's still up to humans to devise... » read more

Debugging Debug


There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more

Tech Talk: 7nm Process Variation


Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. https://youtu.be/WHNjFr1Da6s » read more

Which Verification Engine?


Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

← Older posts