tag: DFY

DTCO/STCO Create Path For Faster Yield Ramps
By Laura Peters - 12 Mar, 2024 - Comments: 0

Higher density in planar SoCs and advanced packages, coupled with more complex interactions and dependencies between various components, are permitting systematic defects to escape traditional detection methods. These issues increasingly are not detected until the chips reach high-volume manufacturing, slowing the yield ramp and bumping up costs. To combat these problems, IDMs and systems co... » read more

Mashup At 7nm
By Ed Sperling - 19 Apr, 2018 - Comments: 0

The merger of two standards organizations typically falls well below the radar of most engineers, but folding the ESD Alliance (formerly known as the EDA Consortium) into SEMI is a different kind of deal. Ever since the introduction of finFETs and multiple patterning, EDA tools have become an integral part of the development of new manufacturing processes. Without those tools, there is no po... » read more

Faster Time To Root Cause With Diagnosis-Driven Yield Analysis
By Mentor, a Siemens Business - 16 Apr, 2015 - Comments: 0

ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed... » read more

Industry Scorecard For 2014
By Brian Bailey - 22 Dec, 2014 - Comments: 0

At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Part one addressed the market and semiconductor areas and in thi... » read more

Making The Right Choices
By Ed Sperling - 21 Feb, 2013 - Comments: 0

FD-SOI at 28nm, or finFETs at 20/14nm? To companies looking at the cost equation, the total market opportunity for SoCs and the NRE required to get there, this is still a manageable formula. It requires lots of number crunching and some unknowns, but by the time you get done with the math it still falls within an acceptable margin of error and the choices are relatively simple. For foundries... » read more

Making Quality A Top Priority in Next-Generation Designs
By Cheryl Ajluni - 25 Jun, 2009 - Comments: 0

By Cheryl Ajluni With system design such a complicated task these days, it is increasingly likely that designers will inadvertently overlook some details of the design process, or worse yet, simply not have the time to address them adequately. Time is readily spent focusing on things like performance, area, timing, and power, but what about something a bit more esoteric in nature—namely, qu... » read more

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