tag: DRAM

Designing AI Hardware To Deal With Increasingly Challenging Memory Wall (UC Berkeley)
By Technical Paper Link - 25 Mar, 2024 - Comments: 0

A new technical paper titled "AI and Memory Wall" was published by researchers at UC Berkeley, ICSI, and LBNL. Abstract "The availability of unprecedented unsupervised training data, along with neural scaling laws, has resulted in an unprecedented surge in model size and compute requirements for serving/training LLMs. However, the main performance bottleneck is increasingly shifting to memo... » read more

DRAM Chip Characterization Study of Spatial Variation of Read Disturbance and Future Solutions (ETH Zurich)
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions" was published by researchers at ETH Zurich. Abstract: "Read disturbance in modern DRAM chips is a widespread phenomenon and is reliably used for breaking memory isolation, a fundamental building block for building robust systems. Row... » read more

The Rising Price Of Power In Chips
By Ed Sperling - 14 Mar, 2024 - Comments: 0

Power is everything when it comes to processing and storing data, and much of it isn't good. Power-related issues, particularly heat, dominate chip and system designs today, and those issues are widening and multiplying. Transistor density has reached a point where these tiny digital switches are generating more heat than can be removed through traditional means. That may sound manageable e... » read more

DRAM Chips Perform Functionally-Complete Boolean Operations (ETH Zurich)
By Technical Paper Link - 12 Mar, 2024 - Comments: 0

A new technical paper titled "Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis" was published by researchers at ETH Zurich. Abstract: "Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog operational properties of DRAM circuitry to enable massively parallel in-DRAM computation. PuD has the potential to significantly ... » read more

Securing DRAM Against Evolving Rowhammer Threats
By Aharon Etengoff - 07 Mar, 2024 - Comments: 0

Advanced process nodes and higher silicon densities are heightening DRAM's susceptibility to Rowhammer attacks, as reduced cell spacing significantly decreases the hammer count needed for bit flips. Rowhammer exploits DRAM’s single-capacitor-per-bit design to trigger bit flips in adjacent cells through repeated memory row accesses. This vulnerability allows attackers to manipulate data, re... » read more

Building Scalable And Efficient Data Centers With CXL
By Lou Ternullo - 15 Feb, 2024 - Comments: 0

The AI boom is giving rise to profound changes in the data center; demanding AI workloads are driving an unprecedented need for low latency, high-bandwidth connectivity and flexible access to more memory and compute power when needed. The Compute Express Link (CXL) interconnect offers new ways for data centers to enhance performance and efficiency between CPUs, accelerators and storage and move... » read more

Re-architecting Hardware For Energy
By Brian Bailey - 15 Feb, 2024 - Comments: 0

A lot of effort has gone into the power optimization of a system based on the RTL created, but that represents a small fraction of the possible power and energy that could be saved. The industry's desire to move to denser systems is being constrained by heat, so there is an increasing focus on re-architecting systems to reduce the energy consumed per useful function performed. Making signifi... » read more

SRAM Scaling Issues, And What Comes Next
By Karen Heyman - 15 Feb, 2024 - Comments: 0

The inability of SRAM to scale has challenged power and performance goals forcing the design ecosystem to come up with strategies that range from hardware innovations to re-thinking design layouts. At the same time, despite the age of its initial design and its current scaling limitations, SRAM has become the workhorse memory for AI. SRAM, and its slightly younger cousin DRAM, have always co... » read more

SW/HW Codesign For CXL Memory Disaggregation In Billion-Scale Nearest Neighbor Search (KAIST)
By Technical Paper Link - 14 Feb, 2024 - Comments: 0

A technical paper titled “Bridging Software-Hardware for CXL Memory Disaggregation in Billion-Scale Nearest Neighbor Search” was published by researchers at the Korea Advanced Institute of Science and Technology (KAIST) and Panmnesia. Abstract: "We propose CXL-ANNS, a software-hardware collaborative approach to enable scalable approximate nearest neighbor search (ANNS) services. To this e... » read more

Memory’s Future Hinges On Reliability
By Karen Heyman - 14 Feb, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the impact of power and heat on off-chip memory, and what can be done to optimize performance, with Frank Ferro, group director, product management at Cadence; Steven Woo, fellow and distinguished inventor at Rambus; Jongsin Yun, memory technologist at Siemens EDA; Randy White, memory solutions program manager at Keysight; a... » read more

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