An Easier Path To Faster C With FPGAs


For most scientists, what is inside a high-performance computing platform is a mystery. All they usually want to know is that a platform will run an advanced algorithm thrown at it. What happens when a subject matter expert creates a powerful model for an algorithm that in turn automatically generates C code that runs too slowly? FPGA experts have created an answer. More and more, the genera... » read more

What’s The Real Benefit Of High-Level Synthesis?


Once upon a time, “behavioral synthesis,” the precursor to high-level synthesis, hung its hat on design productivity as its sole value. By that, I mean, if a behavioral synthesis tool provides a high enough productivity benefit, designers or design managers will boil the ocean to move to it. There was little methodology around it. In fact, even the design entry language was unfamiliar. Yes,... » read more

The Secret To Good Comedy And SystemC Code Verification… Timing!


The High-Level Synthesis (HLS) of algorithmic code, usually written in SystemC, is steadily gaining ground. However, the verification of this code is still a somewhat mixed-up, ad-hoc process. The situation is improving as new techniques are applied, but it is clear that in-the-trenches evaluation of these solutions on real projects is more important right now than grand visions missing substan... » read more

The Secret to Reaching Rapid Verification Closure


Every design team is looking to reduce RTL verification time in order to meet aggressive schedules. Successful teams have moved their level of design abstraction up to the C++ or [gettech id="31018" comment="SystemC"] level and employ [getkc id="105" comment="high-level synthesis"] (HLS) within their design flow. By taking advantage of this high-level description, these teams also plug into int... » read more

System-Level Verification Tackles New Role


Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, VP of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_name="Mentor Gr... » read more

ESL Flow is Dead


It was 20 years ago that Gary Smith coined the term [getkc id="48" comment="Electronic System Level"] (ESL). He foresaw the next logical migration in abstraction up from the [getkc id="49" comment="Register Transfer Level"] (RTL) to something that would be capable of describing and building complex electronic systems. He also saw that the future of EDA depended upon who would control that marke... » read more

ESL: 20 Years Old, 10 To Go


It is a common perception that the rate of technology adoption accelerates. In 1873, the telephone was invented and, after 46 years, it had been adopted by one-quarter of the U.S. population. Television, invented in 1926 took 26 years. The PC in 1975 took just 16 years. It took only 7 years after the introduction of the Internet in 1991 before it was seeing significant levels of adoption. So... » read more

Blog Review: July 22


It's been a hot summer for high-level synthesis, says Cadence's Dave Pursley in a collection of the season's HLS highlights spanning DAC to SystemC Japan. Mentor's Harry Foster continues his survey of functional verification with a look at the adoption trends of various verification technologies, and the reasons one-third of projects use emulation or FPGA prototyping. Synopsys' Navraj Nan... » read more

Does Fast Simulation Help Debug Productivity?


It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by [getentity id="22032" e_name="Cadence"] at the recent Design and Verification Conference (DVCon) in Santa Clara, CA. Brian Bailey, technology editor for Semiconductor Engineer was the moderator for the panel and broke the news to the crowd. Cadence had developed a logic [getkc id... » read more

RTL Power Reduction And High Level Synthesis Report 2013


This report covers trends in the area of low-power design and C-based design. The report analyzes the survey results of 648 engineers and engineering managers and identifies relevant emerging trends. To view this white paper, click here. » read more

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