LPDDR3 controller; Bluetooth 5 RF IP; DisplayPort controllers; discussion on open source and RISC-V; DAC submissions open.
Arastu Systems uncorked a LPDDR3 DRAM Memory Controller. The controller is fully compliant with JEDEC standard JESD209-3C and supports various power down modes as well as multiple channels with a privilege to configure and manage each channel independently and parameterized data width.
CSEM’s Bluetooth Low Energy silicon RF IP has been validated as Bluetooth 5 compatible. RF test equipment supplier Rohde & Schwarz implemented the new Bluetooth functionality in its line of R&S CMW wideband radio communication testers.
Trilinear Technologies launched the fifth generation of its DisplayPort transmitter and reciever link controller cores. The controllers include full support for DisplayPort 1.4 and support a range of implementations. They are currently implemented for evaluation in multiple FPGA platforms.
The ESD Alliance’s Emerging Companies Committee will host a discussion about Open Source and the RISC-V processor Wednesday, January 18, from 6-8:30 p.m. at Cadence Design Systems, Building 10, in San Jose, Calif. The evening features Jim Hogan of Vista Ventures, Rick O’Connor, executive director of the RISC-V Foundation, and Yunsup Lee, SiFive’s chief technology officer. They will describe the path from inception to the open source RISC-V ecosystem, explore whether an open source architecture is appropriate for IoT processing needs and what that means for startups and innovation.
Fortemedia licensed Cadence’s Tensilica Fusion F1 DSP for its next-generation smart microphone processor to support always-on voice trigger and sensor fusion capabilities for voice wake-up in mobile, IoT and consumer applications.
ASolid Technology, a NAND flash controller provider based in Hsinchu, Taiwan, adopted Andes Technology’s AndesCore N9 32-bit CPU core for its AS2726 eMMC chip. ASolid cited savings on area, power and better performance.
Mobileye selected Imagination’s MIPS Warrior I-class I6500 CPU in a coherent, heterogeneous sub-system incorporating NetSpeed’s Gemini cache coherent interconnect IP for a vision-based SoC family designed for image recognition, navigation, and decision making in fully autonomous vehicles.
Faraday expanded its design services to include a virtual prototyping solution based on Synopsys’ Virturalizer.
Retune DSP’s multi-microphone beamforming and echo cancellation technology has been ported and optimized to Cadence’s Tensilica HiFi DSPs for Audio/Voice/Speech. Additionally, Almalence ported their Video SuperSensor video image quality improvement software to the Tensilica Vision DSP.
Architect Specs Harder To Follow
Each new node adds uncertainties and problems, especially at 7nm. Interdisciplinary communication becomes essential.
Embedded Software Verification Issues Grow
Inconsistent results, integration issues, and lack of financial incentives to solve these problems point to continued problems for chipmakers.
What’s Missing In Advanced Packaging
When it comes to multi-board and multi-chips-on-a-board designs, do engineers have all the tools they need?