Why it’s no longer necessary to make a choice.
FPGA Prototyping is more challenging than emulation. Yet for the time invested in prototype setup, developers are rewarded with a validation platform that is capable of running orders of magnitude faster than emulation.
Emulation also has benefits that appeal especially to design verification engineers. Aside from the completely automated compilation and setup flow, it offers robust debugging capabilities and a plethora of interfaces that connect the emulator with various verification environments like HDL Simulators, Virtual Platforms, model based design tools (e.g. Matlab and Simulink) or any other environment capable of C/C++ linking.
But wait, do you really need to choose between emulation and prototyping?
This may have been true in the 1990s, but a lot has changed since then. FPGA technology has evolved and matured as well as FPGA vendor’s synthesis and place & route software. For some reason however, the big-three of EDA keep it separate. The emulation hardware that is based on custom processors or custom FPGAs is extremely expensive and later, if you need to do prototyping for your design bring-up and firmware development, you wind up with investing more in FPGA-based hardware.
Engineers have been working to bridge this gap and unify a hardware platform to be used for both emulation and prototyping as a cost-effective solution. That cost-effectiveness comes from reusability and scalability. Aldec’s offering in this space is based on the latest generation of prototyping boards that contains largest Virtex-7 and now Virtex UltraScale FPGAs from Xilinx. These boards are available in various configurations including the backplane board that delivers the ability to scale the whole system up to 633 million ASIC gates (24 Virtex UltraScale 440 chips). The hardware is precisely designed to meet the most restrictive prototyping criteria for clocks distribution or signal integrity.
From a big picture standpoint, the idea is to reuse the prototyping boards for emulation. The top three requirements are:
The best approach is to use these boards early, when the HDL simulation becomes a verification bottleneck. By applying multiple partitions, as well as incremental synthesis and implementation, turnaround times can be reduced. Emulation probes also need to be matched with signals in RTL code to find what happens in your design and pinpoint the problem. And finally, simulation can be accelerated using either direct signal-level or transaction-level that is based on Accellera’s SCE-MI. You can use SystemC TLM to integrate emulation with the Virtual Platform or other SystemC testbench or regular C/C++ API to connect your emulated design with any other verification environments.
If you’d like to learn more about this topic, may I recommend an article, Why I see C in SCE-MI, written by my colleague, Jacek Majkowski.
Undoubtedly emulation and FPGA Prototyping are converging these days and this process is accelerating due to the tools like Aldec’s HES-DVM. Pure prototyping is still quite difficult to setup when using only FPGA vendor tools, and this is why Aldec is adding prototyping support features to HES-DVM.