3D-IC Intensifies Demand For Multi-Physics Simulation

The introduction of full 3D-ICs will require a simultaneous analysis of various physical effects under different workloads, a step-function change that will add complexity at every step of the design flow, expand and alter job responsibilities, and bring together the analog and digital design worlds in unprecedented ways.

3D-ICs will be the highest-performance advanced packaging option, in some cases reducing the distance that signals need to travel compared to a planar SoC, while also using less power to drive those signals. But with thinner substrates, more concentrated dynamic power density, and enclosed spaces that can trap heat, as well as the potential for noise and other physical effects, getting these devices to work properly will be a massive design challenge.

“There’s always been some level of thermal analysis, but it was done at the end of the design process just to check that nothing got too far out of hand,” said Marc Swinnen, director of product marketing at Ansys. “The design team would target a certain junction temperature and say, ‘Do we meet that junction temperature?’ It was that simple. With multi-die systems, at the RTL floor planning stage, you’re going to have to have some idea of the power output of each of these chips so you don’t arrange them such that two chips get hot at the same mode of operation and are placed right next to each other or right on top of each other. That will doom your design.”

With 3D-ICs, thermal is the primary limiter of integration density. “It’s easy to stack the chips,” said Swinnen. “You can manufacture it, you can design it, but it will never work because it will get too hot. What limits the system density is thermal, and thus thermal has become a very central part to every 3D-IC.”

Heat is just one factor to consider, however. Understanding all the possible interactions requires multi-physics simulation. That involves modeling analog behavior, because a device must cope with a continuum of transistor behavior, not just 0s and 1s.

“The questions that most of the traditional EDA tools address operate at a digital level, when a switch is 0 or 1,” said Ashish Darbari, CEO of Axiomise. “Digital simulation has been around for several decades, employing event-driven simulation techniques. This means the simulation models were event-driven. In the early stages, the stimulus was predominantly directed. In the last two decades, random stimulus generation via OVM/VMM/UVM has become mainstream. What has remained constant is that the models are for the digital domain, not analog. However, the need to assess heat maps to study performance and power, especially for low-power designs, offers new opportunities for EDA, and this is where we are with multi-physics simulation. Multi-physics simulation is used to validate the estimated power density maps and thermal conductivity.”

Heat also can impact the structural integrity of any advanced package, whether it’s 3D-IC, 2.5D, or high-density fan-out. “On a monolithic chip, you never had to worry about structural integrity,” said Ansys’ Swinnen. “Very early on, there were some issues about layers peeling under high acceleration, but that was very minor. These days there are multiple thermal expansions and contractions, in addition to the mechanical construction of chips on chips and on interposers. There are thousands or millions of microbumps that all expand and contract. As the chip warms up, it warps. And because the interposer has been thinned, there are stresses that accompany this. The electronic parameters of a chip change when you stress it mechanically which is actually built into the process. Some transistors are made to be stressed. They’re manufactured in such a way that stress is built into them, and it changes the parameters. Designers of monolithic chips never had to worry about mechanical structural integrity, but now it’s very central to the reliability and robustness of the final product.”

Add to that list electromagnetic coupling and interference, which has always been something high-frequency RF design teams had to deal with. But digital designers typically didn’t have to worry about this in the past. “They stay well below the 5GHz limit where EM really starts becoming important,” Swinnen said. “It’s still high-frequency digital, but traditionally not RF frequency. With high-frequency signals, shorter lines will qualify as the transmission line, and as the frequency gets higher, the shorter the wires are. The signal frequency is the same, but we’ve made the wires a lot longer because on an interposer you’re going four or five inches across an interposer on big interposer multi-die chips. You have digital signals running long distances across these interposers — much longer than they would run on a single chip, so you have to do full electromagnetic analysis of those with inductive coupling, transmission line phenomena — all of those for digital designers. This is another new phenomenon they need to worry about.”

Different approaches, different job responsibilities
As SoCs are decomposed into heterogeneous chiplets, and packaged tightly together in vertical stacks, the number of potential interactions can vary greatly. Being able to simulate those interactions, and to do it early enough to make changes, is required, but those simulations also need to include more elements and behaviors than in the past.

Stephen Slater, EDA product management/integrating manager at Keysight, noted that “multi-physics simulation” suggests everybody is using multiple simulators that all can work within the same environment. “My ‘aha’ moment was realizing it’s not quite as simple as that,” he said. “You have to recognize that there’s true domain expertise – for instance, a mechanical engineer who cares about thermal, versus an electrical engineer who’s maybe very specialized in power amplifier design or some other very specific kind of niche. They have had their entire career using certain tools and are highly productive in those tools. They do not want the needs and requirements of the other engineer to clutter their world. Open, interoperable workflows are needed between tools. Data management is also needed. Let’s say I’m pulling thermal data to use in the electrical engineer’s tool. How do I know I’m pulling the latest data from the latest simulations, or under certain conditions?”

For these reasons, data management tool sets are going to be very important to make this happen. “And then those application specific workflows need to handle these additional domains,” he said. “It’s like saying, ‘Bring the temperature data over, and bring the materials data over so that I can just consume it in my electrical engineer’s tool,’ because they’re not going to be the one who is playing around with different material properties to see if it’s better.”

As the tools change, so will job responsibilities. “When you look at a chip, and you can’t tell how hot a chip will get, you can calculate how much power the chip is putting out,” said Swinnen. “What temperature that brings it to depends where the device is sitting. Do you have it sitting on a cold plate, or is it sitting in the sun in the Sahara? The same chip and same activity will lead to very different temperatures depending on its surroundings, so you have to determine the boundary conditions for your chip. Where does that come from? That’s the system you’re putting the chip in. There’s the packaging, a heatsink, a fan, and is the fan blowing or not? How much heat does it carry away? All of this has to be factored in, even at RTL, to get some sort of idea of what the temperature is going to be. System concerns come in, and when you get into cooling, you’re even into computational fluid dynamics (CFD). There are, however, shortcuts for these things. For instance, a three-fin heatsink will typically dissipate ‘this much’ heat, but those are sort of rough heuristics. As systems get closer to the edge of what’s possible, you need to analyze all of these things. These are all physics that are crashing in on the chip designer, which the monolithic guys traditionally didn’t have to worry about, or was something minor and downstream.”

It’s the chip designers who are starting to worry about these things. “They’re not package or PCB folks,” observed Sutirtha Kabir, senior director for R&D engineering at Synopsys. “Those are very separate domains. These folks are concerned with how to deal with these things. ‘What tools do I use? What flow do you have, EDA vendors, that can help me understand these things? I cannot simply make them, complete them, and then send them to sign-off.’ That doesn’t work anymore.'”

To illustrate the changing dynamics, Keysight’s Slater pointed to a power amplifier found inside a cell phone. “To design a great power amplifier, you want something that is as energy-efficient as possible to extend the battery life, powerful enough to provide the range needed, that works well across all frequency bands required, is stable by design, while keeping signal distortion under control. RFMW engineers have long been designing these amplifiers, tuning the feed networks and control conditions to optimize over all these requirements. With this highly-tuned power amplifier, how does it behave when it starts transmitting? How does it behave when it starts self-heating as the junction temperatures of the transistors in the amplifier start to get hot? The transistor models we are using need to account for this temperature difference. Otherwise, we lose the high accuracy in our modeling that we have come to expect, and cannot predict the behavior of the device. Now, what is the temperature of the junction? That depends on how well we can get heat out of the IC, out of the package, out of the board into the ambient environment.”

This is at the heart of multi-physics, he said. “It’s a recognition that certain domains of expertise — including thermal design, which is usually the mechanical engineers’ responsibility, and electrical design — start to intersect. However, the mechanical engineers’ choice of EDA tools and simulators, are different from the electrical engineers’ choice of tools and simulators.”

Others see similar challenges. Frank Schirrmeister, vice president solutions and business development at Arteris, recalled that at a recent conference he was seated at a table with a system designer, a substrate engineer who deals with interposers, and an engineer who was working on the UCIe PHY. “How much more diverse can things get? We all need to know each other so when we, as a partner, actually bring them into the same room because they haven’t known each other before, each can see why the others are important. So then, how does stuff actually get done? It’s divide-and-conquer. I figure out my latency and my bandwidth from a network on chip (NoC) perspective. I figure out how to pack it into a streaming interface. They figure out, from there, how that is packed into FDI and RDI, the tool interfaces within UCIe to the link layer, which does all the testing, and the PHY layer, which then produces these cool eye charts. Everybody needs to do their job within the specs, and then there is a chance that it actually works. Multi-physics simulation plays a big role in that. Depending on the application domain, depending on where you are, depending on heat and so forth, depending on requirements for automotive and others, you may check for different things at the physical interface. Does it work at -40° C as well as 140° C, because consumer devices have different ranges.

It gets more complicated from here. “Up to now, the digital simulation was just digital simulation,” Schirrmeister said. “Before, it was just reading data sheets. Now, I really want to figure out in an analog simulator how the eye diagrams are forming in my transmission from that end to the other end. And for interoperability checking, I want to simulate that Vendor A PHY can talk to a Vendor B PHY, which is what we are trying to do in the context of chiplet activities, if we ever want to get an open ecosystem. On top of that, you layer things like know you create this amount of data traffic, so now look into the thermal aspects, look into the EM aspects depending on which substrate you’re on. Now you’re adding a whole stack of new complexities on top of it, which, you can try to simulate all together, even though that is not realistic. First, you don’t have all the data typically at the same time. Second, you have all kinds of IP issues putting it together. Third, it takes forever to actually simulate because of the multiple levels of fidelity and simulation granularity. You have a digital clock, and then everything in the analog happens between that clock edge and the next clock edge, so you have myriad cycles to run in simulation before you get even closer to full simulation. The multi-physics simulation space has reacted with parallelization.”

Unifying the flow?
Possibly the biggest challenge — and there are many — is pulling together different tools, as needed, and providing an environment in which they can all work together. This is particularly important for the electrical and thermal domains.

“To do that, we need open interoperable workflows and data management tools to allow the engineers across both domains to quickly grab the latest data for simulation in their realm of specialization,” said Keysight’s Slater. “This can be seen in the design of the power and ground planes in a PCB or package. It begins with making sure we are getting the right DC voltages from the supply to the chips that need them. There will be much more intersection between the engineers who are responsible for the different domains, which then comes back to what the future will look like for EDA. Data management is key. We’ve got to make sure we can get the information we need as quickly as possible from some central resource, and we need to know how to use it.”

Others agree. “Especially when designing chiplets with high-speed interface problems and challenges, there is no one methodology that fits all or covers it all,” said Letizia Giuliano, vice president IP product marketing and management at Alphawave Semi. “When we design these high-speed circuits, such as a 100GB SerDes going on a small chiplet, you have 6 x 6mm, there are 16 lanes of 120 gigabit per second SerDes toggling all the time, and then you have UCIe on the other side that is running at 16 gigabit per second. These are high data rates for single-ended toggling, and then you have single-ended signals. That adds more problems with signal integrity. The way we approach these types of problems is with system-level modeling and statistical modeling. Right now, the major problem we’re trying to solve when we have all this type of SerDes interface, parallel/serial on the die, is how to model with statistical modeling. That is one way of doing it. This was developed in house, and in collaboration with some of our partners, to statistically model our channels to understand all the facets of power in this — jitter, crosstalk, signal integrity, power integrity for all the channels. For us, this is the first level of challenge we’re trying to solve. There is not a single EDA company to solve all these problems so we can just use plug and play.”

As for how to bring multiple types of physics simulations together, many see the industry in an early development phase for solutions — especially when different domain experts in the design team are interested in different types of information during the design process.

“Historically, there’s already been thermal analysis done at the package level,” said John Ferguson, director of product management at Siemens EDA. “They’ll typically look at the die as a uniform material, and it has usually been one die. Now, we’re talking about a lot of them. What they can gain from that is some insight into how the RDL in their package potentially is going to be impacted. But they have to make a lot of guesses, because they don’t know what’s in the die. They don’t know how the die is heating up, which makes things difficult. Beyond that, you also then have multiple chips in there, so you have to think about the mechanical stresses, particularly with respect to some of the thermal impacts.”

Ultimately the industry is concerned about whether this collection of chips or chiplets will function as expected. “Getting color maps and all of that is all fine and good, but at the end of the day the question is, ‘Does this actually work?’ It’s a little bit scary, even if you have known good die that standalone tested out fine on the testbench,” said Ferguson. “But now, when you put them into an assembly, they might not quite meet spec anymore. How do you account for that? How do you plan for that? That’s a nightmare, and that’s what everybody’s trying to solve.”

Complicating matters is that while die stacking has matured significantly in the last five to eight years, it’s still undergoing rapid changes. “The foundries and the OSATs are coming out with new offerings every quarter, so it’s very difficult to predict and model all that when they’re putting the tracks down in front of the train,” noted Joseph Davis, senior director for Calibre interfaces & mPower product management at Siemens EDA. “And the package that you’re using today — your company may not have ever done it. That foundry or OSAT may have done this twice, with some other customer, before they move on to the next thing with another customer. It’s evolving very rapidly, and modeling takes time.”

As a result, engineering team must go back to basics. “You can do more abstraction and do things earlier in the flow,” Davis said. “When you have those models, those can be pushed forward and used earlier in the flow. If you’re finding out the material properties of your package, you know halfway through your project that there are no models for it. You have to simulate it from first principles, and that’s why you get these physics-based simulators. Every package is different. Every stack is different. Just give me the materials properties and we’ll simulate it from there. There’s no compact model or early analysis that you’re going to do.”

Conclusion
When there isn’t a roadmap, the best alternative is to do more analysis and simulation as early as possible.

Synopsys’ Kabir said this includes shifting left. “The classical, ‘I’m finishing design and doing sign-off with analysis engines and it’s not working,’ are things the customers figure out even before they start laying down a single track. You have to estimate cost, and if you’re off, your product line management is going to say, ‘Forget it. This isn’t going to fly.’ So you have to Left Shift. The whole industry has a very sign-off mentality. You take the data out, you go to this analysis engine, and you run it. It’s not inside the implementation cockpit. This left shifting is a must. That’s number one.”

In addition, design teams need to make sense of much more data than in the past, often with the help of machine learning. “It’s not just any AI/ML,” Kabir said. “When you have a potential design space of a million design points, you have to figure out the 200 or 300 you want to run and find the top 5 design points. There must be a very good sandbox that has AI/ML plugged into it very tightly. This is not just writing a script and running it all day long. A human being can’t do that.”

Related Reading
Why There Are Still No Commercial 3D-ICs
More than Moore is off to a good start, but the next steps are a lot more difficult.
3D-ICs May Be The Least-Cost Option
Advanced packaging has evolved from expensive custom solutions to those ready for more widespread adoption.
Next-Gen Power Integrity Challenges
Experts discuss power integrity challenges and best practices in designs at 7nm and below, and in 2.5D and 3D-IC packages.