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Ann Mutschler

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Ann Mutschler is senior executive editor at Semiconductor Engineering.

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Facing Up To Reality
By Ann Mutschler - 10 Feb, 2010 - Comments: 0

Welcome to the world of power awareness. Engineers are well aware that just as timing and area were previously separate considerations in the chip design process, power is also now a top-level consideration. In this blog, we will examine issues related not only to low-power in chip design, but the wide-reaching topic of power-aware design overall. Engineers today must consider the impacts of... » read more

Should Sign-Off And Implementation Be Separate Tools?
By Ann Mutschler - 28 Jan, 2010 - Comments: 0

By Ann Steffora Mutschler In the last stages of design, how data is readied for manufacturing used to be relatively straightforward. Point tools were used to implement the design via a place and route tool then the design was “signed off” with physical verification software. Sign-off is the gate the design goes through before it can go into manufacturing. The design must meet the qua... » read more

Combining Power And Synthesis
By Ann Mutschler - 14 Jan, 2010 - Comments: 0

By Ann Steffora Mutschler Each passing design node shrinks electronic designs ever smaller and more complex, which has made power management a critical design priority – even in the synthesis step in the design flow. Synthesis has always been an integral part of the design process, particularly at the RTL level. But as chip design has become more complicated, the need to raise the pro... » read more

Making DFM Work Better
By Ann Mutschler - 17 Dec, 2009 - Comments: 0

By Ann Steffora Mutschler At 65nm, design for manufacturing optimization and analysis has mostly been an afterthought. At 40nm and beyond, DFM has been pushed well up into the design phase. There are good reasons for this shift. What emerged at the 65nm node were signoff tools that understand manufacturing used in semiconductor design, said Manoj Chako, a product director for digital si... » read more

The Abstraction of Test
By Ann Mutschler - 29 Oct, 2009 - Comments: 0

By Ann Steffora Mutschler By now, semiconductor design abstraction is old hat to many engineers, but mention the term “semiconductor test abstraction” and expect a blank stare in return. Design complexity, enormous design size, and short market windows have put tremendous pressure on test to occur earlier rather than later. Even at the RTL level, where hardware test typically has not ... » read more

End-User Report: Interoperability Still Lacking With System-Level Power Modeling
By Ann Mutschler - 27 Aug, 2009 - Comments: 0

All of the major EDA vendors and standards groups are pitching modeling as the next level of abstraction for advanced process nodes, but is it working as planned for the chipmakers? System-Level Design caught up with Frans Theeuwen, Department Manager for System Design at NXP Semiconductors Corp. to discuss system-level design and power modeling. By Ann Steffora Mutschler SLD: How long has N... » read more

To Bus Or Not To Bus, That Is The Question
By Ann Mutschler - 31 Jul, 2009 - Comments: 0

By Ann Steffora Mutschler When you hear the words, “block interface,” your ears may not perk up, but as system architects well understand, making the right choice between a bus or non-bus interface on an SoC is absolutely critical to design’s success in terms of power efficiency, reusability and performance. How many of the problems in new chip designs have to do with the interconne... » read more

The Argument For Low Power In The Data Center
By Ann Mutschler - 16 Jul, 2009 - Comments: 0

By Ann Steffora Mutschler For budgetary and ‘green’ motives, enterprise IT customers are demanding higher energy efficiency from their servers. This ultimately rests on the shoulders of the processor designer as the MPU is a significant source of power usage. Interestingly, the hidden and ugly truth is that for most data center managers, the cost of electricity for that data center is... » read more

The Impact of 3D Packaging
By Ann Mutschler - 11 Jun, 2009 - Comments: 0

With semiconductor packaging becoming a more crucial piece of the Moore’s Law roadmap, the industry is still sorting out the impact of a 3D design and packaging approach on design time, cost and power. 3D is now commonly used for high volume applications such as cell phones and SD cards, and is accomplished at the packaging step either through chip stacking or package-on-package (PoP) stac... » read more

Hiring Begins Again—Slowly
By Ann Mutschler - 27 May, 2009 - Comments: 0

By Ann Mutschler & Ed Sperling After one of the longest downturns in many decades, hiring has started again in parts of the semiconductor industry. No one would call it a hiring boom, and some companies that have been postponing layoffs are still making cuts, but there is definitely is a change under way. This is evident on some of the job boards, which have postings for engineers with pa... » read more

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