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Ann Mutschler

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Ann Mutschler is senior executive editor at Semiconductor Engineering.

Author's Latest Posts

End-User Report: Interoperability Still Lacking With System-Level Power Modeling
By Ann Mutschler - 27 Aug, 2009 - Comments: 0

All of the major EDA vendors and standards groups are pitching modeling as the next level of abstraction for advanced process nodes, but is it working as planned for the chipmakers? System-Level Design caught up with Frans Theeuwen, Department Manager for System Design at NXP Semiconductors Corp. to discuss system-level design and power modeling. By Ann Steffora Mutschler SLD: How long has N... » read more

To Bus Or Not To Bus, That Is The Question
By Ann Mutschler - 31 Jul, 2009 - Comments: 0

By Ann Steffora Mutschler When you hear the words, “block interface,” your ears may not perk up, but as system architects well understand, making the right choice between a bus or non-bus interface on an SoC is absolutely critical to design’s success in terms of power efficiency, reusability and performance. How many of the problems in new chip designs have to do with the interconne... » read more

The Argument For Low Power In The Data Center
By Ann Mutschler - 16 Jul, 2009 - Comments: 0

By Ann Steffora Mutschler For budgetary and ‘green’ motives, enterprise IT customers are demanding higher energy efficiency from their servers. This ultimately rests on the shoulders of the processor designer as the MPU is a significant source of power usage. Interestingly, the hidden and ugly truth is that for most data center managers, the cost of electricity for that data center is... » read more

The Impact of 3D Packaging
By Ann Mutschler - 11 Jun, 2009 - Comments: 0

With semiconductor packaging becoming a more crucial piece of the Moore’s Law roadmap, the industry is still sorting out the impact of a 3D design and packaging approach on design time, cost and power. 3D is now commonly used for high volume applications such as cell phones and SD cards, and is accomplished at the packaging step either through chip stacking or package-on-package (PoP) stac... » read more

Hiring Begins Again—Slowly
By Ann Mutschler - 27 May, 2009 - Comments: 0

By Ann Mutschler & Ed Sperling After one of the longest downturns in many decades, hiring has started again in parts of the semiconductor industry. No one would call it a hiring boom, and some companies that have been postponing layoffs are still making cuts, but there is definitely is a change under way. This is evident on some of the job boards, which have postings for engineers with pa... » read more

Why Semiconductor Packaging Matters
By Ann Mutschler - 27 May, 2009 - Comments: 0

By Ann Steffora Mutschler After decades of being considered almost an afterthought, semiconductor packaging is emerging as an integral part of the Moore’s Law road map. Power, heat, manufacturing and impurities like soft errors have become so pronounced at 45nm and 32nm that they are actually beginning affect the package. And while these problems are not new, continual shrinking has made th... » read more

Low-Power Standards War
By Ann Mutschler - 13 Mar, 2009 - Comments: 0

To the uninitiated, establishing a technology standard may seem straightforward. In reality, the process is mired with technical and political issues as evidenced by the ongoing battle for a de facto low-power design standard between the Unified Power Format (UPF) and the Common Power Format (CPF).   Currently, UPF is with the IEEE for final ratification as P1801, set for vote this month, ... » read more

Next Steps In Verification IP
By Ann Mutschler - 19 Feb, 2009 - Comments: 0

By Ann Steffora Mutschler With the cost of failure at an astronomical high, the last thing chip designers want to worry about is the physical IP they will use to build their SoC. In addition to less willingness on the customer’s behalf to take risks, complexity and economics have driven the need for more off-the-shelf IP and a corresponding rise in interest in verification IP. Compoundi... » read more

IP Consolidation Improves Reliability
By Ann Mutschler - 22 Jan, 2009 - Comments: 0

By Ann Steffora Mutschler As individual blocks of IP in an IC design grow to more than 1 million gates, making sure each block functions reliably and interfaces with the system properly is a make-or-break scenario for many companies. For one thing, getting it right is absolutely critical as the semiconductor industry reaches its maturity point with margins harder to reach. Coupled with an ind... » read more

The ESL Conundrum
By Ann Mutschler - 17 Dec, 2008 - Comments: 0

As Moore’s Law continues its relentless march, the “electronic system level” (ESL), which is the next higher level of abstraction above the register transfer level (RTL), continues to be adopted as an answer to the ever-increasing complexity of designing semiconductors. Although ESL emerged about five years ago, the term itself still can confound the very community that seeks to embrac... » read more

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