Why The Next Breakthrough In Chips Depends On Rethinking Design Workflows


At this year’s DAC Chips to Systems Conference (DAC 2025), Keysight and its partners showcased how engineers are rethinking design workflows from chips to complete systems. The Partner Theater, hosted by Keysight brought together innovators from across the semiconductor ecosystem – each tackling one of today’s most pressing challenges: how to manage exploding volumes of design data and le... » read more

Semiconductor Metrology: IMMSE For The Rapid ID of Defective Chips (Samsung)


A new technical paper titled "Ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry for semiconductor metrology" was published by researchers at Samsung. Abstract "We propose an ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry (IMMSE) system for semiconductor metrology. The IMMSE system achieves large-area measurements with a 20 mm × 20 mm field of ... » read more

Scaling Nanoribbon Transistors Based on Monolayer 2D Semioconductors (Stanford, HORIBA, SLAC)


A new technical paper titled "Scaling High-Performance Nanoribbon Transistors with Monolayer Transition Metal Dichalcogenides" was published by researchers at Stanford University, HORIBA Scientific, and SLAC National Accelerator Laboratory. Abstract "Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional se... » read more

CDI For The Metrology Of Copper Pads Used In Hybrid Bonding (Paul Scherrer Institute, Samsung)


A new technical paper titled "Coherent diffractive imaging simulations for wafer inspection of periodic structures" was published by researchers at the Paul Scherrer Institute and Samsung. Excerpt "We present a study of phase retrieval algorithms applied to the metrology of copper pad topography for hybrid bonding. We demonstrate that by including a priori information in the update functi... » read more

A Modular System In Package Approach For Automotive Short Range Radar Applications (Ruhr Univ. Bochum, Fraunhofer et al.)


A new technical paper titled “Leveraging Modularity of Chiplets to Form a 4×4 Automotive FMCW-Radar in an eWLB-Package” was published by researchers at Ruhr University Bochum, Fraunhofer Institute, University Bremen, Infineon and WavesenseDD GmbH. Abstract “Dividing a System on Chip (SoC) into multiple smaller chiplets and embedding them into a single package has gained significant t... » read more

Lightweight AI Techniques For Automated Inspection of Silicon Wafers (Fraunhofer)


A new technical paper titled "Towards efficient wafer visual inspection: Exploring novel lightweight approaches for anomaly detection and defect segmentation" was published by researchers at Fraunhofer Portugal AICOS. Excerpt "AI has made significant strides in unsupervised anomaly detection and supervised defect segmentation, yet its application to wafer inspection remains underexplored. T... » read more

Chip Industry Week in Review


Samsung and SK hynix joined OpenAI's Stargate initiative to ensure there will be enough memory chips to meet the needs of AI data centers. The goal is to produce up to 900,000 DRAM wafer starts per month. OpenAI also inked agreements to explore the development of next-gen data centers in Korea. Axcelis Technologies (ion implantation systems) will merge with Veeco Instruments (compound semic... » read more

Distributed Authentication Framework Leveraging Multi-Party Computation In A Scalable Tree-Based Architecture (Univ. of Central Florida, Louisiana State)


A new technical paper titled "AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems" was published by researchers at University of Central Florida and Louisiana State University. Abstract "The rapid adoption of chiplet-based heterogeneous integration is reshaping semiconductor design by enabling modular, scalable, and faster time-to-market s... » read more

New Spectre Branch Target Injection, Spectre-BTI, Attack Primitives On CPUs (ETH Zurich)


A new technical paper titled “VMSCAPE: Exposing and Exploiting Incomplete Branch Predictor Isolation in Cloud Environments” was published by researchers at ETH Zurich. Abstract “Virtualization is a cornerstone of modern cloud infrastructures, providing the required isolation to customers. This isolation, however, is threatened by speculative execution attacks which the CPU vendors att... » read more

Double Duty Logic Block Architecture Enabling Concurrent LUT and Adder Chain Usage (Nanyang Technological Univ. et al)


A new technical paper titled "Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage" was published by researchers at Nanyang Technological University, Cornell University, Altera, University of Waterloo and University of Toronto. Abstract "Flexibility and customization are key strengths of Field-Programmable Gate Arrays (FPGAs) when compared to other computing devices... » read more

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