Smarter Packaging: How AI is Reshaping Assembly and Materials Control

By Gregory Haley - 02 Oct, 2025 - Comments: 0

When a multi-die package worth $500 fails final test because of a defect that originated three process steps earlier, the economics of advanced packaging become painfully clear. Each excursion carries downstream costs that ripple across assembly, final test, and even system qualification. As packaging margins tighten, the industry is betting on artificial intelligence (AI) to catch those pro... » read more

Blog Review: Oct. 1

By Jesse Allen - 01 Oct, 2025 - Comments: 0

Synopsys' Chun-Soo Kim and Hoseong Kim suggest making the entire design flow local layout effect-aware to identify and address issues early and ultimately improve PPA by avoiding overly pessimistic designs. Siemens' Kirk Fabbri explores the power distribution network, focusing on power plane capacitance and how it varies with the dynamic switching characteristics of the load and dielectric c... » read more

How To Cool 3D-ICs

By Ed Sperling - 01 Oct, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how to cool 3D-ICs and what's missing from the tool chain today, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager at Keysigh... » read more

Research Bits: Sept. 30

By Jesse Allen - 30 Sep, 2025 - Comments: 0

Hybrid memory for edge training and inference Researchers from CEA-Leti, Université Grenoble Alpes, CEA-List, the French National Centre for Scientific Research (CNRS), the University of Bordeaux, Bordeaux INP, IMS France, Université Paris-Saclay, and the Center for Nanosciences and Nanotechnologies developed a hybrid memory system that combines the traits of ferroelectric capacitors (FeCAP)... » read more

Security Technical Paper Roundup: Sept. 30

By Linda Christensen - 30 Sep, 2025 - Comments: 0

A number of hardware security-related technical papers were presented at the August 2025 USENIX Security Symposium. The organization provides open access research, and the presentation slides and papers are free to the public. Topics include side-channel attacks and defenses, embedded security, fuzzing, fault injection, rowhammer, and more. Here are some highlights with associated links: [ta... » read more

The Rise Of AI Co-Processors

By Ed Sperling - 29 Sep, 2025 - Comments: 0

Figuring out the best kinds of processors to use for different AI workloads is a challenge. AI algorithms are undergoing rapid and frequent changes, and the workloads tied to them can vary by data type, by user, and sometimes because of software/firmware updates. On top of that, AI computations tend to require much higher utilization rates than traditional computing, and that will only become m... » read more

Preparing For The Multiphysics Future Of 3D-ICs

By Siemens EDA - 29 Sep, 2025 - Comments: 0

3D integrated circuits (3D ICs) are emerging as a revolutionary approach to design, manufacturing and packaging in the semiconductor industry. Offering significant advantages in size, performance, power efficiency and cost, 3D ICs are poised to transform the landscape of electronic devices. However, with 3D ICs come new design and verification challenges that must be addressed to ensure success... » read more

How Multiphysics Is Powering The Future Of 3D-ICs

By John Ferguson - 29 Sep, 2025 - Comments: 0

It’s surprising to learn that the idea of 3D integrated circuits (3D ICs) has been kicking around for over sixty years. Not long after the first MOS IC emerged in 1960, researchers were already thinking vertically. By 1983, Fujitsu manufactured the first 3D IC prototype using through-silicon via (TSV) technology, using laser beam recrystallization. That’s a long time for a good idea to catc... » read more

Voltage Regulation Moves Into The Package

By Bryon Moyer - 29 Sep, 2025 - Comments: 0

Integrated circuits require a variety of voltages and a wide range of currents, typically supplied by voltage regulators. But increasing power density is resulting in higher power delivery losses. Moving those regulators closer to the chips they power can reduce those losses. Co-packaging them holds the most promise, but it comes with challenges. “What people have been talking about, ev... » read more

Chip Industry Week In Review

By The SE Staff - 26 Sep, 2025 - Comments: 0

U.S. Trade Representative Jamieson Greer warned Southeast Asian semiconductor manufacturers that they must shift production to the U.S. or face new punitive tariffs, reports the South China Morning Post. President Trump previously floated a 100% tariff on imported chips. Malaysia and other regional economies are offering large concessions and promises of U.S. goods purchases in hopes of securin... » read more

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