Wafer Warpage Evolution During Key Backside Power Delivery Network Fabrication Steps (Korea Univ., Georgia Tech)


A new technical paper titled "Process-Induced Warpage Behavior in Backside Power Delivery Network Fabrication" was published by researchers at Korea University and Georgia Institute of Technology. Abstract "As semiconductor devices continue to scale, backside power delivery networks (BSPDNs) have emerged as a promising alternative to conventional front-side power delivery networks (FSPDNs),... » read more

Blog Review: Oct. 8


Siemens' Azat Latypov presents a stochastic-aware optical proximity correction strategy that demonstrated an order-of-magnitude reduction in the probability of stochastic defects for both SRAM and logic designs, sacrificing minor edge placement error in return for much lower failure rates. Cadence's Dimitry Pavlovsky introduces the AMBA CHI Chip-to-Chip (C2C) protocol, which extends the CHI ... » read more

How 3D-IC Will Change Chip Design


Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC design challenges and the impact on stacked die on EDA tools and methodologies, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities busine... » read more

Research Bits: Oct. 7


Doping oxide insulator improves SiGe conductivity Researchers from TU Wien, Johannes Kepler University Linz, and TU Bergakademie Freiberg manufactured a silicon-germanium (SiGe) transistor using an alternative approach that involves doping the insulating oxide layer to produce a long-range effect that extends into the semiconductor. Called modulation acceptor doping (MAD), the technique ena... » read more

Chip Industry Technical Paper Roundup: Oct. 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=480 /] Find more semiconductor research papers here » read more

First Stage Of Nanoscale Imaging In Positive-Tone EUV Photoresists: The Impact Of Polymer Sequence (Berkeley Lab, Columbia Hill)


A new technical paper titled "Initial stage of nanoscale imaging in positive-tone extreme UV photoresists: the influence of polymer sequence" was published by researchers at Lawrence Berkeley National Laboratory and Columbia Hill Technical Consulting. Abstract "Photolithographic patterning using extreme ultraviolet (EUV, 92.5 eV) light is a radiolytic process that initially forms electrons,... » read more

In-SRAM Computing Architecture Tailored For Cryptographic Acceleration Within MCUs (UC Riverside)


A new technical paper titled "CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing" was published by researchers at University of California, Riverside. Abstract "Secure communication is a critical requirement for Internet of Things (IoT) devices, which are often based on Microcontroller Units (MCUs). Current cryptographic solutions, which rely on software librari... » read more

Algorithms For Black-Box, Physical-to-DRAM Address-Mapping Recovery (Georgia Tech, CNRS, Et Al.)


A new technical paper titled "Knock-Knock: Black-Box, Platform-Agnostic DRAM Address-Mapping Reverse Engineering" was published by researchers at Georgia Tech, ESILV, CentraleSupelec, Inria, CNRS, IRISA. Abstract "Modern Systems-on-Chip (SoCs) employ undocumented linear address-scrambling functions to obfuscate DRAM addressing, which complicates DRAM-aware performance optimizations and hind... » read more

Silicon IP Continues Steady Growth Path


EDA and silicon IP revenue increased 8.6% to $5.089 billion in Q2 2025, up from $4.6855 billion in Q2 2024, according to the ESD Alliance. Total EDA revenue growth was assisted by impressive results in the CAE category, the largest tool sector, which showed 17.2% growth over Q2 2024. “It was another good quarter overall," said Walden C. Rhines, executive sponsor of the SEMI Electronic Desi... » read more

Chip Industry Startup Funding: Q3 2025


The third quarter of 2025 was dominated by massive rounds for companies developing AI chips and quantum computers. Over $2.5 billion went to AI, with wafer-scale chip maker Cerebras leading the pack with a $1.1 billion raise. While several edge AI companies received backing, the quarter saw a marked shift towards solutions for the data center as firms seek to reduce the cost and power consumpti... » read more

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