Advanced Packaging Limits Come Into Focus

By Gregory Haley - 19 Mar, 2026 - Comments: 0

Key Takeaways: Packaging is now a performance variable. Substrate, bonding, and process sequence determine what can be built at scale. Warpage underlies most advanced packaging failures and gets harder to control as package sizes grow. Every proposed solution, such as glass, panel processing, and backside power, solves one problem while creating another. Moore's Law has shif... » read more

Replay‑based Validation as a Scalable Methodology for Chiplet‑based Systems (Intel, Synopsys)

By Technical Paper Link - 18 Mar, 2026 - Comments: 0

A new technical paper, "ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation," was published by researchers at Intel, Nvidia and Synopsys. Abstract "Integration of CPU and GPU technologies is a key enabler for modern AI and graphics workloads, combining control-oriented processing with massive parallel compute capability. As systems evolve toward chiplet-based archite... » read more

Memory For AI At The Edge

By Ed Sperling - 18 Mar, 2026 - Comments: 0

Inferencing at the edge has very different needs than training large language models or large-scale inferencing in AI data centers. Many edge devices run on a battery. They're price-sensitive, and they are constrained by the physical area of the device. As a result, the amount of memory that can be packed into these devices is also limited. Steve Woo, Rambus fellow and distinguished inventor, t... » read more

From Reactive to Predictive: AI-Driven Optimization for ATE Performance & Reliability

By Cohu - 18 Mar, 2026 - Comments: 0

As ATE systems become increasingly complex and data-intensive, traditional rule-based optimization methods struggle to keep pace. In this Semicon Korea presentation, Cohu's Wai-Kong Chen will be exploring how artificial intelligence enables a paradigm shift from reactive troubleshooting to predictive and self-optimizing ATE systems. Read more here. Fig.1: Sweet spot inference. Sourc... » read more

Blog Review: Mar. 18

By Jesse Allen - 18 Mar, 2026 - Comments: 0

Cadence's Jamdagni Trivedi explains the UALink Protocol Level Interface, which defines how devices exchange data and control information, and shares insights into its structure, functionality, and significance in multi-node accelerator systems. Synopsys' Dustin Todd argues that AI sovereignty will be defined by and built on strategic interdependence, where countries develop and retain meanin... » read more

Identifying Read Disturbance Threshold of DRAM Chips (ETH Zurich, Rutgers)

By Technical Paper Link - 17 Mar, 2026 - Comments: 0

A new technical paper, "DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips," was published by ETH Zurich and Rutgers University. Abstract "State-of-the-art DRAM read disturbance mitigations rely on the read disturbance threshold (RDT) (e.g., the number of aggressor row activations needed to induce the first read disturba... » read more

Analysis of the Evolving Landscape of Ultra-low-power Edge AI Processors (U. of Austria, ETH Zurich)

By Technical Paper Link - 17 Mar, 2026 - Comments: 0

A new technical paper, "Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review," was published by University of Austria and ETH Zurich. Abstract "This review examines the rapidly evolving landscape of ultra-low-power edge processors, covering heterogeneous Systems-on-Chips (SoCs), neural accelerators, near-sensor and in-sensor architectures, and emerging dataflow a... » read more

How AI Will Automate Chip Design

By Ed Sperling - 17 Mar, 2026 - Comments: 0

AI has been used in EDA for many years for the core algorithms in tools, but it's getting smarter and more optimized with the rollout of generative and agentic AI. As it evolves and improves, hardware engineers are finding ways to leverage it for more complex tasks. Ziyad Hanna, corporate vice president at Cadence, talks about five levels of autonomy in chip design that mirror those in the auto... » read more

Human-Centered Agentic AI Workflows For RTL Verification

By Siemens EDA - 17 Mar, 2026 - Comments: 0

Productivity challenges in modern semiconductor development stem less from individual tool limitations and more from process-level complexity across design creation, verification, and iteration. Agentic EDA addresses this shift by embedding intelligence directly into workflows that span creation and validation. The Questa One Agentic Toolkit extends the Questa One solution with human-centere... » read more

Optimizing Oxide Interfaces To Preserve Device Performance in TMDC-based Transistors (imec, ETH Zurich)

By Technical Paper Link - 17 Mar, 2026 - Comments: 0

A new technical paper, "Oxide induced degradation in MoS2 field-effect transistors," was published by researchers at imec and ETH Zurich. Abstract excerpt "Transition Metal Dichalcogenides (TMDC) are promising candidates for future scaled transistor channels but their performance is often degraded by imperfections such as the interface with amorphous gate oxides. This study examines how amo... » read more

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