Research Bits: Mar. 17
By Jesse Allen - 17 Mar, 2026 - Comments: 0

Photonic ski jumps Researchers from Massachusetts Institute of Technology (MIT), MITRE, University of Arizona, and Sandia National Laboratories developed a new class of photonic devices that enable the precise broadcasting of light from a chip into free space. The chip uses an array of microscopic structures that curl upward, resembling tiny ski jumps, and allows control over how light is e... » read more

3D DRAM with CBA Technology (Georgia Tech)
By Technical Paper Link - 16 Mar, 2026 - Comments: 0

A new technical paper, "System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures," was published by researchers at Georgia Tech. Abstract "3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery, which may degrade sensing margin, laten... » read more

Systematic Training and Validation of AI-based Systems With Digital Twins and Scenario Engineering
By Technical Paper Link - 16 Mar, 2026 - Comments: 0

A new technical paper, "Towards Structured Training and Validation of AI-based Systems with Digital Twin Scenarios," was published by researchers at RWTH Aachen University and RIF e.V. Abstract "Artificial intelligence (AI) has emerged as a pivotal technology for autonomous systems across various domains, but quality assurance remains challenging due to limited training data and inadequate ... » read more

Pathfinding Method That Models ECC Overhead for Chiplet Interconnects (UCLA)
By Technical Paper Link - 16 Mar, 2026 - Comments: 0

A new technical paper, "Link Quality Aware Pathfinding for Chiplet Interconnects," was published by researchers at UCLA. Abstract "As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energy per bit, reach, and raw bit error rate (BER). Meeting stringent delivered BER ... » read more

AI Design Reshapes Data Management
By Ann Mutschler - 16 Mar, 2026 - Comments: 0

Key takeaways: Integrating AI into chip workflows is pushing companies to overhaul their data management strategies, shifting from passive storage to active, structured, and machine-readable systems. As training and inference workloads grow, data movement, congestion, and energy efficiency become the dominant challenges, often surpassing raw compute capability. Proprietary and comple... » read more

Chip Industry Week In Review
By The SE Staff - 13 Mar, 2026 - Comments: 0

Disruptions caused by the Iran conflict have taken about one third of the global helium supply off the market, an essential gas for semiconductor manufacturing, reports the World Economic Forum. Other potential impacts for the chip industry include bromine and other chemical shortages, logistical disruptions, and higher energy prices incurred by fabs in Asia. Top Deals IBM and Lam R... » read more

HBM4E Raises The Bar For AI Memory Bandwidth
By Nidish Kamath - 12 Mar, 2026 - Comments: 0

The pace of AI innovation continues to expose a painful reality. Compute keeps scaling, but memory bandwidth remains one of the hardest bottlenecks to remove. As AI models grow larger and more complex, feeding data fast enough into accelerators has become just as critical as raw compute capability. High Bandwidth Memory (HBM) has been central to solving this challenge, and the next step in that... » read more

Human-Centered Agentic AI Comes To RTL Verification
By Harry Foster - 12 Mar, 2026 - Comments: 0

For decades, productivity gains in electronic design automation (EDA) came from better engines. Faster solvers, higher-capacity simulators, and more scalable formal tools allowed design and verification teams to keep pace as designs grew larger. That model is no longer sufficient. Today’s design and verification bottleneck is not raw tool performance, but the coordination overhead required... » read more

CPO Is Extending The Limits Of What’s Possible In AI Data Centers
By Ann Mutschler - 12 Mar, 2026 - Comments: 0

Key Takeaways I/O architecture must be co-designed with compute from day one. Partitioning SoCs into heterogeneous chiplets (compute, EIC, PIC, lasers) directly affects power delivery, floor-planning, interconnect topology, and system scalability. Successful CPO designs require architects to think in multi-physics terms, balancing electrical signaling, thermal stability, optical beha... » read more

Rethinking Voice AI At The Edge: A Practical Offline Pipeline
By Odin Shen - 12 Mar, 2026 - Comments: 0

Cloud-based AI dominates the headlines, but responsive and private interaction lies at the edge. This blog post shows how to build a fully offline, real-time voice assistant using the Arm-based NVIDIA DGX Spark platform. The system integrates open-source components such as faster-whisper and vLLM. It delivers low-latency, human-like dialogue without sending data outside the local environment. ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy