Serial Wire Debug (SWD) Protocol: Efficient Debug Interface For Arm-Based Systems


Modern embedded systems are becoming increasingly compact, power efficient, and feature rich. As SoCs integrate more functionality, developers need reliable debug access without increasing pin count or board complexity. Serial Wire Debug (SWD) addresses these needs by providing a streamlined alternative to JTAG, enabling high performance debug features using only two pins, making it ideal for t... » read more

AI Power on the Edge


Key takeaways Power and thermal become primary design considerations, not just optimizations. Hardware architectures need to be developed from the ground up. Hardware/software/model co-development is essential. Implementing AI on the edge is driven by a different set of metrics than training or even inference in the cloud. It makes power a first-class citizen, if not the mos... » read more

Scale Up, Scale Out Get a New Partner


Key Takeaways: Three AI data center scaling strategies are scale-up, scale-out, and scale-across. Scale-up is within a rack; scale-out is between racks; scale-across is between data centers. Each of the three uses a different interconnect strategy to optimize either latency or jitter. As today’s data center workloads — especially for AI and HPC — outgrow the physical, ... » read more

Customizing Foundation IP For Ultra-Low-Voltage Designs


By Daryl Seitzer, Andrew Appleby, and Mohammad Tanveer Building a new system-on-chip (SoC) starts with assembling the right foundational elements—pre‑verified IP for logic, memory, I/O, and other essential functions. Standard IP solutions typically address most common design needs, but some projects call for more specialized approaches, especially when innovation is critical or when t... » read more

Neuromorphic Computing Platform In Perovskite Nickelates (UCSD, Rutgers)


A new technical paper, "Protonic nickelate device networks for spatiotemporal neuromorphic computing," was published by researcher at UCSD and Rutgers University. Abstract "Computation in biological neural circuits arises from the interplay of nonlinear temporal responses and spatially distributed dynamic network interactions. Replicating this richness in hardware has remained challenging... » read more

Data-Driven Optimization In Semiconductor Manufacturing


Effectively scaling semiconductor manufacturing is critical to meeting the rapidly growing demand and requires solving numerous technical challenges. The substantial capital investment required for semiconductor manufacturing further complicates the business equation. Legacy fabs are designed redundantly to maintain the uptime required for reliable ROI, further increasing costs. Producers want ... » read more

Improving Yield Through Shared Data


Increasing complexity due to advanced packaging, multi-die assemblies, and more devices under test is having an impact on yield, which in turn slows time to market and impacts overall chip costs. What's needed is a way to share data that previously was siloed by chipmakers, fabs, and OSATs. Jayant D'Souza, technical product director at Siemens EDA, talks about the underlying drivers for sharing... » read more

Accelerating 4D Imaging Radar with Vision 4DR


4D imaging radar enhances automotive sensing by adding elevation to traditional range, velocity, and azimuth measurements. This enables better target detection and classification, enabling safer driving decisions. Multiple input multiple output (MIMO) antenna technology has expanded the role of radar sensing from tracking moving targets to high-resolution imaging of the surroundings. High... » read more

Security in Data Centers for AI Applications


AI data centers are the engines of the new data revolution, transforming data lakes and extracting meaningful insights guided by user queries. In this white paper, we revisit the security problem and highlight that AI data centers pose specific risks whose impact extends far beyond initial expectations. Starting from the premise that the AI is “only as good as the data that comes in/out”, w... » read more

FeFETs With Laminated Gate Stacks For Radiation Resilience in Vertical NAND (Georgia Tech)


A new technical paper, "Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack," was published by researchers at Georgia Tech. Abstract "NAND flash forms the core of modern solid-state storage, which is critical for data-intensive AI applications, yet charge-trap NAND suffers rapid threshold-voltage (Vth) degradation under ionizing radiation, causi... » read more

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