CPU Fuzzing Via Intricate Program Generation (ETH Zurich)


A technical paper titled “Cascade: CPU Fuzzing via Intricate Program Generation” was published by researchers at ETH Zurich. Abstract: "Generating interesting test cases for CPU fuzzing is akin to generating programs that exercise unusual states inside the CPU. The performance of CPU fuzzing is heavily influenced by the quality of these programs and by the overhead of bug detection. Our a... » read more

Light-Matter Interaction In Van Der Waals Nanophotonic Devices


A technical paper titled “Deeply subwavelength integrated excitonic van der Waals nanophotonics” was published by researchers at University of California Los Angeles, University of Washington Seattle, and Auburn University. Abstract: "The wave nature of light sets a fundamental diffraction limit that challenges confinement and control of light in nanoscale structures with dimensions signi... » read more

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs (Kyungpook National University)


A technical paper titled “Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs” was published by researchers at Kyungpook National University. Abstract: "Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and sp... » read more

Research Bits: October 31


Skinlike sensor for robots University of British Columbia engineers with help from researchers from Frontier Robotics, Honda research institute, created a soft sensor that approximates skin. Mostly made of silicone rubber, the sensor uses weak electric fields to sense objects, even at a distance, and can detect forces into and along its surface. The sensor could provide touch sensitivity and d... » read more

Chip Industry’s Technical Paper Roundup: October 31


New technical papers added to Semiconductor Engineering’s library this week. [table id=159 /] More Reading Technical Paper Library home » read more

What Will That Chip Cost?


In the past, analysts, consultants, and many other experts attempted to estimate the cost of a new chip implemented in the latest process technology. They concluded that by the 3nm node, only a few companies would be able to afford them — and by the time they got into the angstrom range, probably nobody would. Much has changed over the past few process nodes. Increasing numbers of startups... » read more

Unlocking The Power Of Edge Computing With Large Language Models


In recent years, Large Language Models (LLMs) have revolutionized the field of artificial intelligence, transforming how we interact with devices and the possibilities of what machines can achieve. These models have demonstrated remarkable natural language understanding and generation abilities, making them indispensable for various applications. However, LLMs are incredibly resource-intensi... » read more

Analyzing The U.S. Advanced Packaging Ecosystem With Countermeasures To Mitigate HW Security Issues


A technical paper titled “US Microelectronics Packaging Ecosystem: Challenges and Opportunities” was published by researchers at University of Florida, University of Miami, and Skywater Technology Foundry. Abstract: "The semiconductor industry is experiencing a significant shift from traditional methods of shrinking devices and reducing costs. Chip designers actively seek new technologica... » read more

Progress In The Fabrication Of CMOS Devices Based On Stacked 2D TMD Nanoribbons (Intel)


A technical paper titled “Process integration and future outlook of 2D transistors” was published by researchers at Intel Corporation. Abstract: "The academic and industrial communities have proposed two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a future option to supplant silicon transistors at sub-10nm physical gate lengths. In this Comment, we share the r... » read more

Optimization Of The Interface Between The PD And The AFE In High-Speed, High-Density Optical Receivers


A technical paper titled “Optimizing the Photodetector/Analog Front-End Interface in Optical Communication Receivers” was published by researchers at University of Toronto. Abstract: "This article addresses the optimization of the interface between the photodetector (PD) and the analog front-end in high-speed, high-density optical communication receivers. Specifically, the article focuses... » read more

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