Week In Review: Semiconductor Manufacturing, Test


TSMC is delaying construction on its $40 billion fab in Arizona due to a shortage of U.S. semiconductor workers and higher-than-expected expenses, Bloomberg reported. The Semiconductor Industry Association (SIA) urged the U.S. government to refrain from further restrictions on semiconductor technology to China “until it engages more extensively with industry and experts to assess the impac... » read more

Week In Review: Design, Low Power


Cadence will acquire Rambus' SerDes and memory interface PHY IP business. Rambus will retain its digital IP business, including memory and interface controllers and security IP. “With this transaction, we will increase our focus on market-leading digital IP and chips and expand our roadmap of novel memory solutions to support the continued evolution of the data center and AI,” said Sean Fan... » read more

A Flip-Chip, Co-Packaged With Photodiode, High-speed TIA in 16nm FinFET CMOS


A technical paper titled "A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes" was published by researchers at University of Toronto, Alphawave IP, and Huawei Technologies Canada. Abstract: "A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude... » read more

NoC Obfuscation For Protecting Against Reverse Engineering Attacks (U. Of Florida)


A technical paper titled "ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks" was published by researchers at University of Florida. Abstract: "Modern System-on-Chip designs typically use Network-on-Chip (NoC) fabrics to implement coordination among integrated hardware blocks. An important class of security vulnerabilities involves a rogue foundry reverse-engineeri... » read more

A Practical DRAM-Based Multi-Level PIM Architecture For Data Analytics


A technical paper titled "Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics" was published by researchers at Korea Advanced Institute of Science & Technology (KAIST) and SK hynix Inc. Abstract: "Processing-in-memory (PIM) architecture is an inherent match for data analytics application, but we observe major challenges to address when accelerating it usi... » read more

A Chiplet-Based Supercomputer For Generative LLMs That Optimizes Total Cost of Ownership


A technical paper titled "Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models" was published by researchers at University of Washington and University of Sydney. Abstract: "Large language models (LLMs) such as ChatGPT have demonstrated unprecedented capabilities in multiple AI tasks. However, hardware inefficiencies have become a significant factor limiting ... » read more

A Hardware Accelerator Designed For The Homomorphic SEAL-Embedded Library


A technical paper titled "VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library" was published by researchers at University of Pisa. Abstract: "Homomorphic Encryption (HE) allows performing specific algebraic computations on encrypted data without the need for decryption. For this reason, HE is emerging as a strong privacy-preserving solution... » read more

Gallium Oxide Flash Memory (KAUST & IIT)


A technical paper titled "Demonstration of β-Ga2O3 nonvolatile flash memory for oxide electronics" was published by researchers at King Abdullah University of Science and Technology (KAUST) and Indian Institute of Technology. Abstract: "This report demonstrates an ultrawide bandgap β-Ga2O3 flash memory for the first time. The flash memory device realized on heteroepitaxial β-Ga2O3 film... » read more

Topological Semimetal Synthesized Thin Film That Can Increase Power and Memory Storage While Using Less Energy


A technical paper titled "Robust negative longitudinal magnetoresistance and spin-orbit torque in sputtered Pt3Sn and Pt3SnxFe1-x topological semimetal" was published by researchers at University of Minnesota. Abstract: "Contrary to topological insulators, topological semimetals possess a nontrivial chiral anomaly that leads to negative magnetoresistance and are hosts to both conductive bulk ... » read more

A 3D MEMS Coaxial Socket Overcomes Challenges In Semiconductor Package Chip Testing


A technical paper titled "Fabrication and Characterization of Three-Dimensional Microelectromechanical System Coaxial Socket Device for Semiconductor Package Testing" was published by researchers at Yonsei University and Protec MEMS Technology. Abstract: "With the continuous reduction in size and increase in density of semiconductor devices, there is a growing demand for contact solutions tha... » read more

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