Challenges In Backside Power Delivery

By Laura Peters - 17 Nov, 2022 - Comments: 0

One of the key technologies to enable scaling below 3nm involves delivering of power on the backside of a chip. This novel approach enhances signal integrity and reduces routing congestion, but it also creates some new challenges for which today there are no simple solutions. Backside power delivery (BPD) eliminates the need to share interconnect resources between signal and power lines on t... » read more

High-NA EUV Complicates EUV Photomask Future

By Jan Willis - 17 Nov, 2022 - Comments: 0

The eBeam Initiative’s 11th annual Luminaries survey in 2022 reported EUV fueling growth of the semiconductor photomask industry while a panel of experts cited a number of complications in moving to High-NA EUV during an event co-located with the SPIE Photomask Technology Conference in late September. Industry luminaries representing 44 companies from across the semiconductor ecosystem partic... » read more

Hot Trends In Semiconductor Thermal Management

By Karen Heyman - 17 Nov, 2022 - Comments: 1

Increasing thermal challenges, as the industry moves into 3D packaging and continues to scale digital logic, are pushing the limits of R&D. The basic physics of having too much heat trapped in too small a space is leading to tangible problems, like consumer products that are too hot to hold. Far worse, however, is the loss of power and reliability, as overheated DRAM has to continually r... » read more

Creating Airgaps To Reduce Parasitic Capacitance In FEOL

By Sumant Sarkar - 17 Nov, 2022 - Comments: 0

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the effective dielectric constant of the material layers between the gate and source/drain. This can be done by creating airgaps in the dielectric material at that location. This type of work has been do... » read more

Heterogeneous Chip Assembly Helps Optimize Medical And Wearable Devices

By Dick Otte - 17 Nov, 2022 - Comments: 0

Heterogeneous integration (HI) has significant implications for the medical, health, and wearables industry. At Promex, we utilize a variety of complex assembly processes to achieve HI for medical and biotech applications. This post will take a closer look at the processes associated with assembling these classes of devices. Figure 1 provides a high-level overview of our approach. Nearly eve... » read more

Where All The Semiconductor Investments Are Going

By Ed Sperling - 17 Nov, 2022 - Comments: 2

Companies and countries are funneling huge sums of money into semiconductor manufacturing, materials, and research — at least a half-trillion dollars over the next decade, and maybe much more — to guarantee a steady supply of chips and know-how to support growth across a wide swath of increasingly data-centric industries. The build-out of a duplicate supply chain that can guarantee capac... » read more

Wall Street View Of EDA Industry

By Bob Smith - 17 Nov, 2022 - Comments: 0

Jay Vleeschhouwer, managing director of Griffin Securities, has followed the electronic design automation (EDA) industry as a leading financial analyst for 25 years and is a popular speaker at the annual Design Automation Conference (DAC). I spoke with Vleeschhouwer after attending his presentation "The State of EDA: A View from Wall Street" at this year’s DAC. Bob Smith: According t... » read more

On-Chip Power Distribution Modeling Becomes Essential Below 7nm

By Ann Mutschler - 16 Nov, 2022 - Comments: 0

Modeling power distribution in SoCs is becoming increasingly important at each new node and in 3D-ICs, where tolerances involving power are much tighter and any mistake can cause functional failures. At mature nodes, where there is more metal, power problems continue to be rare. But at advanced nodes, where chips are running at higher frequencies and still consuming the same or greater power... » read more

Blog Review: Nov. 16

By Jesse Allen - 16 Nov, 2022 - Comments: 0

Siemens EDA's Jake Wiltgen explains the difference between transient and permanent faults when designing to the ISO 26262 standard, including where they come from and key ways to protect against them. Synopsys' Vikas Gautam points to how the economics of designing large SoCs is driving chiplet-based designs and the need for die-to-die standards such as UCIe, along with the key protocol verif... » read more

Multiexpert Adversarial Regularization For Robust And Data-Efficient Deep Supervised Learning

By Samsung - 16 Nov, 2022 - Comments: 0

Deep neural networks (DNNs) can achieve high accuracy when there is abundant training data that has the same distribution as the test data. In practical applications, data deficiency is often a concern. For classification tasks, the lack of enough labeled images in the training set often results in overfitting. Another issue is the mismatch between the training and the test domains, which resul... » read more

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