Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract:  "The expansive globalization of the semiconductor supply chain has introduced numerous untrusted entities into different stages of a device’s lifecycle, enabling them to compromise its security. To make matters worse, the increasing complexity in the design as well as aggressive time-to-market requirements of the newer generation of integrated circuits can lead either designers t... » read more

Advances in Logic Locking: Past, Present, and Prospects
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract: "Logic locking is a design concealment mechanism for protecting the IPs integrated into modern System-on-Chip (SoC) architectures from a wide range of hardware security threats at the IC manufacturing supply chain. Logic locking primarily helps the designer to protect the IPs against reverse engineering, IP piracy, overproduction, and unauthorized activation. For more than a decade,... » read more

Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Intellectual property (IP) cores are essential to creating modern system-on-chips (SoCs). Protecting the IPs deployed in modern SoCs has become more difficult as the IP houses have been established across the globe over the past three decades. The threat posed by IP piracy and overuse has been a topic of research for the past decade or so and has led to creation of a field called wat... » read more

Interfacial ferroelectricity in marginally twisted 2D semiconductors
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Twisted heterostructures of two-dimensional crystals offer almost unlimited scope for the design of new metamaterials. Here we demonstrate a room temperature ferroelectric semiconductor that is assembled using mono- or few-layer MoS2. These van der Waals heterostructures feature broken inversion symmetry, which, together with the asymmetry of atomic arrangement at the interface of tw... » read more

Software-Driven and System-Level Tests Drive Chip Quality
By Bryon Moyer - 08 Mar, 2022 - Comments: 0

Traditional semiconductor testing typically involves tests executed by automatic test equipment (ATE). But engineers are beginning to favor an additional late-test pass that tests systems-on-chip (SoCs) in a system context in order to catch design issues prior to end-product assembly. “System-level test (SLT) gives a high-volume environment where you can test the hardware and software toge... » read more

Addressing The ABF Substrate Shortage With In-Line Monitoring
By Wesley Chou - 08 Mar, 2022 - Comments: 1

Ajinomoto build-up film (ABF) substrate has been a key component in chip manufacturing since its introduction shortly before the turn of the millennium. Substrates made with Ajinomoto build-up film – an electrical insulator designed for complex circuits – are found in PCs, routers, base stations, and servers. Looking ahead, the ABF substrate market will continue to grow, with revenue up ... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II
By Rahul Singhal - 08 Mar, 2022 - Comments: 0

By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

Auto Chipmakers Dig Down To 10ppb
By Anne Meixner - 08 Mar, 2022 - Comments: 0

How do engineers deliver 10 defective parts per billion (Dppb) to auto makers if they only screen 1 million parts per year? Answer: By comprehending failure mechanisms and proactively screening for them. Modern automobiles contain nearly 1,000 ICs that must perform over the vehicle’s life (15 years). This drives quality expectations ever higher. While 10 Dppm used to be a solid benchmark, ... » read more

Enabling Silicon Lifecycle Solutions
By Aileen Ryan - 08 Mar, 2022 - Comments: 0

The concepts of product lifecycle management (PLM) should be familiar, although the semiconductor industry has yet to adopt a system for managing the entire lifecycle of a product from inception through design, realization, deployment, and field service, right through to end-of-life activities such as final disposal. Now, a combination of business and technical pressures is bringing PLM capabil... » read more

Improving Performance And Simplifying Coding With XY Memory’s Implicit Parallelism
By Synopsys - 08 Mar, 2022 - Comments: 0

Instruction-level Parallelism (ILP) refers to design techniques that enable more than one RISC instruction to be executed simultaneously in the same instruction, which boosts processor performance by increasing the amount of work done in a given time interval, thereby increasing the throughput. This parallelism can be explicit, where each additional instruction is explicitly part of the instruc... » read more

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