Marangoni Effect-Based Under-Layer For A Dual Damascene Via-First Approach

By Brewer Science - 19 Aug, 2021 - Comments: 0

One of the main challenges of a Dual Damascene (DD) via-first process is the control of the Critical Dimensions (CDs) in the lithography of the trenches. The PhotoResist (PhR) thickness presents variations from the via arrays to the open areas, which cause the variation of CDs: the swing effect. The planarization of a DD via-first process is reported. A dual-layer solution is used to demonst... » read more

Always On, Always At Risk

By Ed Sperling - 18 Aug, 2021 - Comments: 0

Always-on devices are everywhere, and each of them is a potential target for hackers. While many people associate always-on devices with smart speakers such as an Amazon Alexa or Google Home, or a connected security camera, that's only one component in a system. There's a broader infrastructure behind those devices. So even if you power down a digital assistant/smart speaker, everything it's... » read more

Wafer-Level Fan-Out For High-Performance, Low-Cost Packaging Of Monolithic RF MEMS/CMOS

By Amkor - 18 Aug, 2021 - Comments: 0

Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging [1]. Wafer-level fanou... » read more

Blog Review: Aug. 18

By Jesse Allen - 18 Aug, 2021 - Comments: 0

Arm's Charlotte Christopherson explores the possibilities of flexible, non-silicon electronics with the creation of PlasticArm, an ultra-minimalist Cortex-M0-based SoC that, even with just 128 bytes of RAM and 456 bytes of ROM, is twelve times more complex than previous flexible electronics. Cadence's Claire Ying highlights the importance of integrity and data encryption (IDE) technology for... » read more

Process Variation Analysis Of Device Performance Using Virtual Fabrication — Methodology Demonstrated On A CMOS 14-nm FinFET Vehicle

By Coventor - 18 Aug, 2021 - Comments: 0

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. W... » read more

Working With RISC-V

By Ed Sperling - 17 Aug, 2021 - Comments: 0

RISC-V is coming on strong, but working with this open-source processor core isn't as simple as plugging in a commercial piece of IP. Zdenek Prikryl, CTO at Codasip, talks about utilizing hypervisors and open source tools and extensions to the RISC-V instruction set architecture, where design teams can run into problems, what will change as the architecture becomes more mature, the difference b... » read more

Manufacturing Bits: Aug. 17

By Mark LaPedus - 17 Aug, 2021 - Comments: 0

Scaling qubits Australia is a hotbed of R&D activity, especially in the field of quantum computing. For example, the University of New South Wales (UNSW) in Australia has demonstrated a possible way to control millions of qubits in a silicon quantum chip. Researchers from UNSW Sydney have devised a new three-dimensional dielectric resonator, a technology that could deliver controlled... » read more

Power/Performance Bits: Aug. 17

By Jesse Allen - 17 Aug, 2021 - Comments: 0

Digital fiber Researchers at MIT, Harrisburg University of Science and Technology, and Rhode Island School of Design developed a digital fiber that can sense, store, analyze, and infer activity after being sewn into a shirt. "This work presents the first realization of a fabric with the ability to store and process data digitally, adding a new information content dimension to textiles and a... » read more

Impact Of GAA Transistors At 3/2nm

By Brian Bailey - 16 Aug, 2021 - Comments: 2

The chip industry is poised for another change in transistor structure as gate-all-around (GAA) FETs replace finFETs at 3nm and below, creating a new set of challenges for design teams that will need to be fully understood and addressed. GAA FETs are considered an evolutionary step from finFETs, but the impact on design flows and tools is still expected to be significant. GAA FETs will offer... » read more

Implementing Improved Security And Connectivity For The Smart Home

By Steve Hanna - 16 Aug, 2021 - Comments: 0

The smart home continues to evolve in available functions and complexity as several different connectivity protocols from numerous suppliers target a variety of products for use in smart homes. However, many consumers (71% according to incontrol) acknowledge fear of their personal information being stolen while using smart home products. At the same time, ease of use for user-installed products... » read more

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