Week In Review: Manufacturing, Test

By Mark LaPedus - 28 Aug, 2020 - Comments: 0

Trade As reported, the U.S. recently implemented more restrictions on U.S. chip sales to Huawei. In response, SEMI has released the following statement in response to the new export control rule changes announced by the U.S. Commerce Department: “SEMI recognizes the role of export control measures to address threats to U.S. national security. However, we are very concerned the new export ... » read more

Week In Review: Design, Low Power

By Jesse Allen - 28 Aug, 2020 - Comments: 0

Tools & IP Monozukuri unveiled its IC/Package co-design tool, GENIO. GENIO integrates existing silicon and package EDA flows to create full co-design and I/O optimization of complex multi-chip designs. It works seamlessly across all existing EDA flows and comprises floor planning, I/O planning and end-to-end interconnect planning combined with cross-hierarchical pathfinding optimization.... » read more

Understanding Advanced Packaging Technologies And Their Impact On The Next Generation Of Electronics

By Sandy Wen - 28 Aug, 2020 - Comments: 2

Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip to encompassing a growing number of schemes for interconnecting multiple types of chips. Advanced packaging has become integral to embedding increased functionality into a variety of electronics, such as cellular phones and self-driving vehicles, by supporting high device density in ... » read more

Week In Review: Auto, Security, Pervasive Computing

By SE Staff - 28 Aug, 2020 - Comments: 0

Pervasive computing — data center, edge, IoT Marvell is working on silicon for the data infrastructure market using TSMC’s 5nm process node. Marvell says it has multiple designs already under contract for its 5nm portfolio across the carrier, enterprise, automotive, and data center markets. The first products are sampling by the end of next year. Ansys’ multiphysics signoff tools, R... » read more

Confusion Persists In Verification Terms

By Brian Bailey - 27 Aug, 2020 - Comments: 7

I find it amazing that an area of technology that attempts to show, beyond a reasonable doubt, that a design will work before it is constructed can be so bad at getting some basic things right. I am talking about verification terminology. I have been in this industry for over 40 years and it is not improving. In fact, it is getting worse. The number of calls I have with people where they hav... » read more

The Power Of Visualization

By Hagai Arbel - 27 Aug, 2020 - Comments: 2

In the 1990s, the National Semiconductor Israeli site in Herzliya was responsible for the design and verification of the company’s flagship RISC processor. That was the place and the time when the concept of constraint-random, abstract, coverage-driven verification was born. Engineers realized that without a random generation of stimuli opcodes, it would be very hard to fully verify new pr... » read more

The Four Pillars Of Hyperscale Computing

By Frank Schirrmeister - 27 Aug, 2020 - Comments: 0

In his keynote at CadenceLIVE Americas 2020, Facebook’s Vijay Rao, director, Technology and Strategy, described the four core elements the team considers when designing their data centers—compute, storage, memory, and networking. Wait a minute. Facebook? How did we get here? Wasn’t EDA supposed to be focused on chip design? As indicated in a previous blog, electronic value chains are defi... » read more

Understanding The Performance Of Processor IP Cores

By Roddy Urquhart - 27 Aug, 2020 - Comments: 1

Looking at any processor IP, you will find that their vendors emphasize PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider performance. The first thing to think about is what aspect of performance you care about. Do you care more about the ... » read more

Challenges In Using AI In Verification

By Ann Mutschler - 27 Aug, 2020 - Comments: 0

Pressure to use AI/ML techniques in design and verification is growing as the amount of data generated from complex chips continues to explode, but how to begin building those capabilities into tools, flows and methodologies isn't always obvious. For starters, there is debate about whether the data needs to be better understood before those techniques are used, or whether it's best to figure... » read more

Assessing Synchronization And Graphics-Compute-Graphics Hazards

By Gerry Raptis - 27 Aug, 2020 - Comments: 0

In modern rendering environments, there are a lot of cases where a compute workload is used during a frame. Compute is generic (non-fixed function) parallel programming on the GPU, commonly used for techniques that are either challenging, outright impossible, or simply inefficient to implement with the standard graphics pipeline (vertex/geometry/tessellation/raster/fragment). In gener... » read more

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