Reliability Monitoring Of GUC 7nm High-Bandwidth Memory (HBM) Subsystem


This white paper presents the use of proteanTecs’ Proteus for HBM subsystem reliability based on deep data analytics and enhanced visibility, overcoming the limitations of advanced heterogeneous packaging. It will describe the operation concept and provide results from a GUC 7nm HBM Controller ASIC. A typical CoWoS chip has hundreds of thousands of micro-bumps (u-bumps). 3-8 u-bumps are us... » read more

Week In Review: Manufacturing, Test


Chipmakers Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. There are already signs that the foundries have pushed out their 3nm production schedules. So, expect 7nm and 5nm to become long-running nodes. At 3nm, Samsung and TSMC are going in different directions. Samsung is developing a gate-all-around (GAA) technology called nanosheet FETs. TSMC will e... » read more

Week In Review: Auto, Security, Pervasive Computing


PCs get work-from-home bump Rather than using Intel chips, Apple will be making its own chips for its Mac computers, using Arm cores, Bloomberg reports. TSMC will manufacture the chips. Intel, meanwhile, was up 14% quarter year-over-year its PC business, which it attributes to more people working from home and needed new equipment. Despite a strong quarter, however, the company pulled its 2... » read more

Capturing Bugs Visually


This paper presents a new way to comprehend complex scenarios, in order to significantly accelerate bug detection and resolution. By defining a new visual language, which creates interaction vertices between the simulation scenarios and the code structure on a single matrix, we offer a novel way to compare multiple cycles. It enables verification engineers to reach solid conclusions regarding a... » read more

Week In Review: Design, Low Power


Tools & IP Codasip unveiled its Codasip SweRV Core EH1 Support Package, which provides support for Western Digital's open source RISC-V-based core. The support package provides a comprehensive set of tools and components needed to design, implement, test, and write software for a SweRV Core-based SoC with support for leading EDA open and commercial flows. A free basic version is available ... » read more

A Node Too Far?


Physics is an unforgiving master. While the semiconductor industry has been actively developing new transistor structures, new materials for interconnects and lining trenches, and new approaches to alleviate congestion at the lowest metal levels, it also has been playing an accelerating game of Whac-a-Mole. Whenever a problem pops up, the solution to that problem is never complete and more prob... » read more

5G Brings New Verification Challenges


In the summer of 2018, Siemens raised a few eyebrows within the verification community when we acquired Sarokal, based in Finland. What that community did not piece together at the time was that Sarokal is the leader in 5G testing and has a seasoned team of people that have work closely with leading telecommunication companies to provide hardware and software solutions for fronthaul system test... » read more

Analog Design Needs To Change


It’s an exciting time to be involved in analog design! Innovation in analog design methodology has been flourishing with the introduction of new tools and improved methodologies. And this innovation is badly needed; analog design is getting tougher. Design schedules remain tight, and the technical challenges analog designers face continue to grow – especially when moving to advanced node te... » read more

Math And Electronic Design Automation


Even though our teenage children may not show it the proper appreciation (yet), math is often referred to as the "universal language." And it is, even in EDA. Whenever I’m asked what the heck I do in my day job, I often fall back on analogies—a lot of them refer to building houses. For the geekier ones among us, I have even invoked The Hitchhiker's Guide to the Galaxy's Slartibartfast to ex... » read more

The Debug Problem…


While semiconductor verification techniques have evolved considerably over the last 25 years, the debug of design problems found during verification has barely changed. New algorithms including machine learning, visualization approaches, and problem-solving ideas allow a different approach to debugging that saves up to an order of magnitude in debug time. Since the inception of Hardware Desc... » read more

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