Constraint-Based Verification Of Clock Domain Crossings


There are many measures of the ever-growing size and complexity of semiconductor devices: die area, transistor count, gate count, size of memories, amount of parallel processing and more. All these factors mean more time spent in design, but they also have a major impact on verification. Since virtually all industry studies show verification time and effort growing faster than design, this impa... » read more

Intelligent System Design


Electronics technology is proliferating to new, creative applications and appearing in our everyday lives. To compete, system companies are increasingly designing their own semiconductor chips, and semiconductor companies are delivering software stacks, to enable substantial differentiation of their products. This trend started in mobile devices and is now moving into cloud computing, automotiv... » read more

What Machine Learning Can Do In Fabs


Semiconductor Engineering sat down to discuss the issues and challenges with machine learning in semiconductor manufacturing with Kurt Ronse, director of the advanced lithography program at Imec; Yudong Hao, senior director of marketing at Onto Innovation; Romain Roux, data scientist at Mycronic; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. L-R:... » read more

Blog Review: March 25


Rambus' Steven Woo checks out common memory systems that are used in the highest performance AI applications and points to the differences between on-chip memory, HBM, and GDDR. Mentor's Colin Walls considers whether software for embedded systems should be delivered as a binary library or source code and warns of some key potential issues when requesting source code. A Synopsys writer poi... » read more

Manufacturing Bits: March 24


Autonomous microscopes FLEET, also known as the ARC Centre of Excellence in Future Low-Energy Electronics Technologies, has developed an autonomous scanning probe microscopy (SPM) technology. SPM is an instrument that makes use of an atomically sharp probe. The probe is placed in close proximity above the surface of a sample. With the probe, the SPM forms images of the surface of the sample... » read more

Building A Safety Verification Flow


Sal Alvarez, senior manager of application engineering at Synopsys, explains how safety verification differs from functional verification, what changes with failure mode effects analysis, and how to determine and verify the effectiveness of safety features. » read more

Power/Performance Bits: March 24


Backscatter Wi-Fi radio Engineers at the University of California San Diego developed an ultra-low power Wi-Fi radio they say could enable portable IoT devices. Using 5,000 times less power than standard Wi-Fi radios, the device consumes 28 microwatts while transmitting data at a rate of 2 megabits per second over a range of up to 21 meters. "You can connect your phone, your smart devices, ... » read more

Speeding Up Verification Using SystemC


Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

Memory Issues For AI Edge Chips


Several companies are developing or ramping up AI chips for systems on the network edge, but vendors face a variety of challenges around process nodes and memory choices that can vary greatly from one application to the next. The network edge involves a class of products ranging from cars and drones to security cameras, smart speakers and even enterprise servers. All of these applications in... » read more

Week In Review: Manufacturing, Test


The coronavirus (COVID-19) continues to have an impact on most, if not all, industries. This includes the electronics, semiconductor and related segments. International Data Corp. (IDC) has released a report on the company’s view on the impact the COVID-19 virus will have on the semiconductor market. The report provides a framework to evaluate the market impact through four scenarios. "... » read more

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