Divided On System Partitioning
By Brian Bailey - 30 Jan, 2020 - Comments: 0

Building an optimal implementation of a system using a functional description has been an industry goal for a long time, but it has proven to be much more difficult than it sounds. The general idea is to take software designed to run on a processor and to improve performance using various types of alternative hardware. That performance can be specified in various ways and for specific applic... » read more

Verification Planning And Management With Formal
By Tom Anderson - 30 Jan, 2020 - Comments: 0

Over the last twenty years, formal verification has grown from a niche technology practiced only by specialists to an essential part of mainstream chip development. Along the way, several advances were needed to make wider adoption of formal feasible. These included the standardization of assertion languages, enhanced formal engine performance and capacity, better debug capabilities, and pushbu... » read more

Making Sure RISC-V Designs Work As Expected
By Ann Mutschler - 30 Jan, 2020 - Comments: 0

The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure devices based on the RISC-V ISA work as expected is proving as hard, if not harder, than other commercially available ISA-based chips. The general consensus is that open source lacks the safety net of commercially available IP and tools. Characterization tends to be generalized, ra... » read more

2019 – The Year Of The “Dynamic Duo” Of Emulation and Prototyping
By Frank Schirrmeister - 30 Jan, 2020 - Comments: 0

In technology, we are always trying to figure out when we have reached critical mass, have crossed the chasm, or even can be considered mainstream. We all have seen the adoption curves for consumer products. In design and verification technology, a distinct B2B setting with fewer end customers than in the B2C domain, the situation seems to be even worse as there is no “one flow” to design a... » read more

Big Design, IP and End Market Shifts In 2020
By Brian Bailey - 30 Jan, 2020 - Comments: 0

EDA is on a roll. Design starts are up significantly thanks to increased investment in areas such as AI, a plethora of new communications standards, buildout of the Cloud, the race toward autonomous driving and continued advancements in mobile phones. Many designs demand the latest technologies and push the limits of complexity. Low power is becoming more than just reducing wasted power at t... » read more

Evaluating NVMe SSD Multi-Gigabit Performance
By Igor Gorokhov - 30 Jan, 2020 - Comments: 0

The multi-channel parallelism and low-latency access of NAND flash technology have made Non-Volatile Memory express (NVMe) based SSDs very popular within the main segments of the data storage market, including not only the consumer electronics sector but also data center processing and acceleration services, where the key role is played by specialized FPGA-based hardware for application-specifi... » read more

Renesas Solves High-Level Verification Challenges Using Formal Equivalence Checking
By Mentor, a Siemens Business - 29 Jan, 2020 - Comments: 0

A team at Renesas Electronics Corporation found that they were significantly reducing the time advantages of their High-Level Synthesis flow due to bugs in their SystemC code and equivalence problems due to design changes. It was taking too much time to find and debug these issues and some bugs were slipping into the generated RTL. To solve these challenges, they added SLEC®, which is the form... » read more

Aligning Automotive Safety Requirements Between IP And SoCs
By Synopsys - 29 Jan, 2020 - Comments: 0

Today’s SoCs for automotive safety-related systems integrate numerous IP blocks. At the system level, the Hardware Software Interface (HSI) between these IP blocks needs to be verified in simulation and validated in prototype. However, the scaling of the scope and effort to verify or validate is not linear based on the growing complexity of SoCs and their components such as IP. Depending on t... » read more

Addressing IC Security Threats Before And After They Emerge
By Ed Sperling - 29 Jan, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss different approaches to security with Warren Savage, research scientist in the Applied Research Laboratory for Intelligence and Security at the University of Maryland; Neeraj Paliwal, vice president and general manager of Rambus Security; Luis Ancajas, marketing director for IoT security software solutions at Micron; Doug Suerich, product evangelist... » read more

Blog Review: Jan. 29
By Jesse Allen - 29 Jan, 2020 - Comments: 0

Mentor's Shivani Joshi introduces the basics of PCB layout and the importance of being familiar with a manufacturer's specs. Cadence's Paul McLellan takes a look at why Design Technology Co-Optimization is increasingly necessary as 3nm approaches and new transistor types like CFET and gate-all-around are on the horizon. Synopsys' Sai Karthik Madabhushi recounts an alarming incident that h... » read more

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