Disaggregation solves some problems, but it creates new ones.
The rising cost and complexity of developing chips at the most advanced nodes is forcing many chipmakers to begin breaking up that chip into multiple parts, not all of which require leading edge nodes. The challenge is how to put those disaggregated pieces back together.
When a complex system is integrated monolithically — on a single piece of silicon — the final product is a compromise among the thermal budget constraints of the component devices.
3D NAND needs high-temperature polysilicon, for example, but the temperatures required degrade the performance of CMOS logic.
Disaggregating memory and logic to separate wafers allows manufacturers to optimize each technology independently. Heterogenous integration becomes even more attractive as sensors, transceivers, and other non-CMOS elements are added to the mix.
The problem is how to connect all the pieces. Monolithic integration depends on well-established backend-of-line (BEOL) metallization processes. When components are packaged separately, manufacturers turn to ball grid arrays and similar designs. But when two or more dies are assembled into a single package, the processes used to connect them lie in a poorly defined middle ground between the two.
Many system-in-package designs rely on solder connections. Pick-and-place tools place pre-bumped singulated dies on an interposer or directly on a destination wafer. Reflow ovens complete the solder bonds in a single high-throughput step. The softer solder material serves as a compliant layer, too, smoothing out height variations that might otherwise degrade the bond quality.
Unfortunately, solder-based technology does not scale to the very high density connections that image sensors, high-bandwidth memory, and similar applications demand. The bonding process flattens and squeezes solder bumps, so the ultimate footprint of the bond is slightly larger than the bump pitch. As that pitch goes down, there simply isn’t room for enough solder to make a robust connection. In work presented at the 2019 International Wafer-Level Packaging Conference, Guilian Gao and colleagues at Xperi estimated that the minimum viable pitch for solder-based integration is about 40 microns.
Cu-Sn solder joints are further limited by poor mechanical properties, which contribute to cracks, fatigue failures, and electromigration. The industry is seeking an alternative solid-state bonding technology to facilitate further pitch scaling, but not many processes can match the high speed, low cost, and flexibility of solder bonding.
For example, whatever bonding scheme is chosen must be able to accommodate height variations in bond pads and interposers. The process temperature also must be low enough to protect all components of the device stack. When packaging schemes involve multiple layers of interposers and attached chips, the base layer faces especially challenging thermal requirements. Each layer above the base may require a separate bonding step.
One proposed alternative, copper-copper direct bonding, has the advantage of simplicity. With no intervening layer, temperature and pressure fuse the top and bottom pads into a single piece of metal, making the strongest possible connection. That’s the idea behind thermocompression bonding. Copper pillars on one die match pads on a second die. Heat and pressure drive diffusion across the interface to make a permanent bond. Typical temperatures in the range of 300 ºC soften the copper, allowing the two surfaces to conform to each other. Thermocompression bonding can take 15 to 60 minutes, though, and requires a controlled atmosphere to prevent copper oxidation.
Clean surfaces stick together
A closely related technique, hybrid bonding, attempts to prevent oxidation by embedding the metal in a dielectric layer. In a damascene process reminiscent of wafer interconnect metallization, electroplated copper fills in holes cut into the dielectric. CMP removes excess copper, leaving bond pads that are recessed relative to the dielectric. Placing the two dielectric surfaces in contact creates a temporary bond.
In work presented at the 2019 IEEE Electronic Components and Technology Conference, researchers at Leti demonstrated the use of a water drop to facilitate alignment. The Xperi group explained that this bond is strong enough to allow manufacturers to assemble a complete multi-chip stack.
The dielectric bond encapsulates the copper, preventing oxidation and allowing the bonding equipment to use an ambient atmosphere. To form a permanent bond, manufacturers turn to an anneal that takes advantage of copper’s larger thermal expansion coefficient. Confined by the dielectric, the copper is forced to expand at its free surface, bridging the gap between the two dies. Copper diffusion then forms a permanent metallurgical bond. In a complex stack, a single anneal step can bond all of the component chips at once. Relatively low annealing temperatures are sufficient in the absence of a native oxide or other barrier.
The height of the bond pads is defined by CMP, a mature, well-controlled process. For all of these reasons, wafer-to-wafer hybrid bonding has been used in applications like image sensors for several years. Wafer-to-wafer bonding applications require pad alignment between the wafers and depend on high device yields to minimize losses. Defective dies on the two wafers are unlikely to line up, so a defect on one wafer can cause the loss of a corresponding good chip on the matched wafer.
Die-to-wafer and die-to-interposer hybrid bonding can potentially open a larger application space, allowing complex heterogenous systems in a single package. However, these applications also require more complex process flows. While wafer-to-wafer and die-to-wafer (or interposer) processes place similar demands on the CMP step and on the bond itself, handling singulated chips post-CMP is more challenging. The manufacturing line has to be able to control the particles produced by the inherently messy singulation step, avoiding voids and other bonding defects.
Related
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The approach offers huge performance gains, but pitfalls remain.
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It has been over 6 years since SONY first started using the Ziptronix developed Cu – Cu diffusion bonding to make their Camera modules. Then the ownership of the technology changed hands. What is the registration error and yield at say 10 um I/O pitch when dies are stacked ( to emulate HBM ) ? What are the defects and root causes ? How sensitive is the 2 step Cu – Cu joint formation to co planarity and cleanliness of the CMP ed surfaces ? The HBM manufacturers ( Sam, SK ) keep using Cu – Sn u Pillar Thermocompression bonding even though finer pitch Cu – Cu would make a lot of sense for them. Although Intel, TSMC etc. now have Hybrid Cu – Cu at pitch of 10 um or so in their roadmap, they cannot give up on Cu – Sn uPillar FC just yet ( a quarter century since we invented it at Motorola and put it into Robotic HVM for Cell Phones ), not for the next few years.