Can We Measure Next-Gen FinFETs?

After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology.

Metrology, the science of measurements, is used to characterize tiny films and structures. It helps to boost yields and prevent defects in the fab, which in turn impacts the overall cost for chipmakers. At advanced nodes, though, metrology is becoming more complex, challenging and expensive. And there are a growing number of gaps in metrology, especially for finFETs at 10nm and beyond.

Existing metrology tools are more than capable of measuring structures in two dimensions. With 3D finFETs, though, the structures are sometimes at the atomic level, where the measurements are well below an angstrom. (One angstrom equals 0.1nm.)

“As devices went from planar to 3D, the metrology requirements became like alligators in the water,” said David Fried, chief technology officer at Coventor. “It becomes a lot harder to measure things on sidewalls and other parts of the device. At the same time, you went to multi-patterning, so you had to measure stuff that really wasn’t where the design said the shapes would be.”

For finFETs, there is no single tool type that can handle all metrology requirements. The complexity of the structures requires a growing assortment of tool types, based on electron beam, optical, X-ray and others.

While today’s metrology tools work, many are reaching their physical limit and/or are too slow. Several next-generation metrology tools are in the works, but they are still in R&D.

“Metrology techniques of all types are challenged to provide sufficient sensitivity for early detection (and) prevention,” said Archita Sengupta, a senior technologist at Intel, during a presentation at SEMI’s recent Strategic Materials Conference.

All told, the issues in metrology can lead to unwanted excursions in the fab. An excursion is a departure from the expected result of a given process step. “We need to reduce excursions,” Sengupta said. “Customers want zero excursions because one issue can have a very large financial impact.”

The challenges
For decades, the industry has made and sold chips based on traditional planar processes. Although planar devices use trailing-edge processes, there is a revival for these chips in several segments, such as automotive, IoT and wireless.

“If you look at the big picture, there are three basic vectors people are working on,” said James Truchard, president and chief executive of National Instruments, during a recent conference call. “One is the data rates. We all want to get our videos faster. We don’t want our neighbors interfering with our videos. (In addition), things like autonomous vehicles will require much faster response times. And then, of course, we talk about billions of Internet of Things at really low power that can stay online for years.”

Meanwhile, there is also plenty of action at the leading-edge nodes. At 20nm, though, planar devices hit the wall due to short-channel effects. To solve the problem, chipmakers introduced finFETs at 22nm and 16nm/14nm. In finFETs, the control of the current is accomplished by wrapping a gate around on each of the three sides of a fin.

FinFETs bring new challenges to the party, however. For example, 16nm/14nm finFETs require double patterning. “Process control, and overlay alignment accuracy, of lithography is extremely stringent,” said Kurt Huang, senior director of corporate marketing at UMC. “Inline inspection and metrology are also extremely important, as the critical dimensions are near the range of a few nanometers. Contaminant control and defect inspection are also crucial for successful mass production.”

Huang noted that 14nm/16nm finFETs need extra strain materials to improve device performance, such as SiGe, which requires additional mask layers. “The control of fin shape, dimension, dosage of ion implantation, and CMP uniformity are all integral parts to ensure local device variation and uniformity across the wafer,” he said. “All of the variation parameters and process controls are critical for achieving high yield.”

Needless to say, metrologists face some new and major challenges at 16nm/14nm and beyond. In addition to being 3D structures, finFETs incorporate a growing number of new materials.

“As a result, characterization/metrology of a multitude of solid state properties is now required,” said Paul van der Heide, senior manager and deputy director at GlobalFoundries, during a presentation at last year’s International Conference on Frontiers of Characterization and Metrology for Nanoelectronics (FCMN). “Examples of some of the properties of interest include structural dimensions, surface roughness, surface/interface chemistry, film composition, distributions of dopants and other minor/trace elements, bonding, phase, grain size, crystal orientation, strain, etc.”

The challenges will increase at 5nm. At that node, chipmakers may migrate from finFETs to a next-generation transistor technology called gate-all-around, which is a finFET on its side with a gate wrapped around it. The channels consist of nanowires.

“The next step in the 3D device evolution will make metrology even more difficult,” Coventor’s Fried said. “Nanowires, and especially stacked nanowires, will have a lot of critical dimensions, which are non-visible from the top. This is going to get ugly.”

The solutions—CD metrology
How will the industry measure finFETs at 10nm and beyond? And what about next-generation transistors?

According to a recent presentation from GlobalFoundries, a multitude of metrology tools will be needed in five basic areas—dimensional, compositional, dopant, strain, and electrical.

For decades, metrologists have used various equipment to take dimensional measurements. Basically, dimensional measurements involve the critical dimensions (CDs) of a structure, such as height, width and spacing.

Planar devices require six different CD measurements. In comparison, finFETs require 12 or more different CD measurements, such as the gate height, fin height and sidewall angle. Each of those also requires different measurements.

Generally, chipmakers are using a technology called scatterometry for the bulk of the CD measurements for the fins. Scatterometry is an optical CD (OCD) technology. It measures the changes in the intensity of light in a device.

Scatterometry is relatively fast, but there are some drawbacks. OCD is a model-based technique. The tools don’t measure the actual device. Instead, they measure a model, or scribe structure, that represents and behaves like the actual device. The measurements between the model and the actual devices are supposed to match or correlate.

“The fin height and profile have become critical. That’s what drove OCD,” said Kevin Heidrich, senior vice president of applications and strategy at Nanometrics, in a recent presentation. “The big challenge is that you need good science to build good models. You need good substrates to validate your models. It’s a chicken and egg problem.”

Fig. 1: 3D device road map. Source: Nanometrics.

OCD is used for some but not all layers. For example, the critical-dimension scanning electron microscope (CD-SEM) is being used for “gate over the fin” applications, according to Ofer Adan, global product manager at Applied Materials, in a recent interview.

Using a focused beam of electrons to generate signals at the surface, the CD-SEM takes a top-down image of a structure. Recently, CD-SEM suppliers added tilt-beam capabilities to the tool. Now, the system can not only take top-down images, but it can also look at structures from an angle. So for finFETs, CD-SEMs can handle fin heights, widths and sidewall angles, but it still cannot measure other parameters.

Still, the CD-SEM is making inroads in other areas. “Critical roughness measurements become more important,” said Mari Nozoe, general manager of the Strategic Business Development Department at Hitachi High-Technologies. “This means the CD-SEM has opportunities to get layers around the finFETs and transistors.”

All told, metrologists will require not one but several CD tools for finFETs. This also includes atomic force microscopy (AFM), which uses a tiny probe to enable measurements.

In fact, many see a scenario where different tools work together. “OCD is able to enhance its performance when combined with CD-SEM,” Nozoe said.

This falls under the category of hybrid metrology. In hybrid, chipmakers use multiple metrology techniques and combine the data. “Hybrid metrology will become a necessity,” Coventor’s Fried said. “Many of these techniques are model-based, so you may need to use two types of metrology to reduce the number of floating parameters to a tractable number.”

Compositional challenges
CD metrology is challenging, but the compositional part of the equation is also difficult. Basically, the compositional segment involves film thickness measurements and the composition of those films.

The problems began to mount when the industry moved from planar to finFETs. For example, in planar, the etch tool may produce a two-dimensional structure, and so the etch team in the fab worries about the CDs of a structure. Then, in a separate module, the deposition teams are dealing with planar films and film thickness issues.

In finFETs, though, the films are buried in fins and trenches. So, the films are topological or three-dimensional in nature. All told, there is an intersection taking place between CD metrology and film thickness measurements.

For this, the separate etch and deposition teams must now work together to solve what’s becoming a mounting problem. At advanced nodes, chipmakers may require some 100 separate thin film measurements just for the development stage alone, according to experts.

As a result, metrologists must throw a number of tools at the problem. “In terms of thin-film measurements like thickness, composition, strain and crystalline structures, various kinds of inline metrological tools, like spectroscopic ellipsometry, XRD, XRF and XRR (are used),” said Han Jin Lim, a technical staff member at Samsung Semiconductor’s R&D Center.

Like scatterometry, ellipsometry is an optical-based technique that uses models. Today’s tool, dubbed the variable-angle spectroscopic ellipsometer, measures wavelengths from the ultraviolet range to near infrared. It measures the thickness and composition of films.

XRD, XRF and XRR are X-ray metrology technologies. Generally, optical metrology is faster than X-ray, but it has some resolution limits. In comparison, X-ray metrology can handle the difficult measurements, although the throughputs are limited.

“For some applications, (X-ray metrology) will deliver higher fidelity measurements,” Coventor’s Fried said. “But I don’t think it’s a cure-all. It’s going to be a matching game between structures and processes with the metrology techniques that provide the highest value.”

Both optical and X-ray are used in conjunction for several applications. For example, chipmakers must measure the high-k/metal-gate structures in finFETs. A typical gate stack can have five to seven layers, according to GlobalFoundries and KLA-Tencor.

Defects are problematic for these structures. And the thickness control limits for these films are 0.4 to 0.6 angstroms, according to the companies.

For this application, metrologists use spectroscopic ellipsometry. Some tools use a xenon arc lamp, which is limited in terms of signal-to-noise capabilities.

For finFETs, ellipsometry needs a boost. Recently, KLA-Tencor moved from an arc lamp to a laser-sustained plasma source, enabling a better signal-to-noise ratio. “That will make it brighter,” said Kartik Venkataraman, senior product marketing manager at KLA-Tencor. “It will also shift the peak of that power distribution to be more UV. That enables a lot of improvements in terms of what we can do for bandgap estimates.”

At times, ellipsometry uses planar film targets, which have limited correlation capabilities. “If you are only using monitor wafers or traditional film pads, then you don’t have an accurate assessment of what your film looks like on the device,” Venkataraman said. “And therefore, the correlation to the electrical performance starts to go away.”

In response, KLA-Tencor moved towards a “films-on-gratings” technique. This, in turn, measures films on proxy targets that closely resemble the device. “Now, we are talking about film thickness measurements on the target of interest,” he said.

Still, the traditional tools aren’t quite enough, so for some measurements in high-k/metal-gate, chipmakers use X-ray reflectivity (XRR), an X-ray metrology technique used for thin-film measurements. Other X-ray metrology tools are also making inroads in the fab. For example, some are taking two X-ray techniques—X-ray fluorescence (XRF) and X-ray photoelectron spectroscopy (XPS). Those are combined using a hybrid approach.

XRF, according to EAG, “is a non-destructive technique that is used to quantify the elemental compositions of materials and to measure film thickness and composition.” Meanwhile, XPS is a surface-sensitive spectroscopic technique that measures the elemental composition.

The XRF/XPS tool provides the measurement of copper lines, including line width and depth. “XPS defines line width due to its much shallower probe depth, which when fed into the XRF (copper) volume data allows the (copper) line depth to be extracted,” GlobalFoundries’ van der Heide said in a paper.

Strain, dopants and electrical
Besides the CDs and films, chipmakers also must worry about another critical part of the finFET—strain materials. Using epitaxial tools, a strain material based on silicon-germanium (SiGe) is grown on the source and drain regions for PMOS.

For this, chipmakers use another X-ray technology, dubbed high-resolution X-ray diffraction (HRXRD). HRXRD is used to explore single-crystal and thin film materials.

Fig. 2: XRXRD is used to measure strain, thickness, composition and lattice relaxation of epitaxial layers. Source: Bruker/Jordan Valley

In another application, HRXRD is also one of the metrology candidates for the channel materials, namely SiGe, for 7nm. In addition, OCD is also competing in the arena.

“Given past history, I’d be hesitant at saying optical will run out of steam,” said Paul Ryan, general manager at Bruker Semiconductor’s X-ray metrology unit in the U.K. “However, the advantage of HRXRD and one of the key parameters is the strain state of the material, and the composition of the epi. The epi tends to be much thicker than traditional SiGe. So, it becomes opaque, meaning optical techniques cannot be used.”

Fig. 3: Where OCD fits in. Source: Nanometrics.

Meanwhile, if that isn’t enough, chipmakers must look at two other parts of the metrology flow—dopants and electrical. For dopants, some use low energy electron induced X-ray emission spectrometry (LEXES). This is used for ultra-shallow implants.

Electrical involves several capacitance-voltage (CV) measurements. And going forward, the list of metrology tools continues to grow in the lab and the fab.

Then, in R&D, the industry has been working on small-angle X-ray scattering (CD-SAXS). This promising technology measures tiny structures, but it suffers from an inadequate power source.

Other technologies are also in R&D. To be sure, though, the industry needs new breakthroughs amid a challenging business climate.

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