200mm Demand Surges

By Mark LaPedus - 17 Dec, 2020 - Comments: 1

A surge in demand for various chips is causing shortages for select 200mm foundry capacity as well as 200mm fab equipment, and it shows no signs of abating in 2021. Foundry customers will face a shortfall of 200mm capacity at select foundries at least in the first half of 2021, and perhaps beyond. Those customers will need to plan ahead to ensure they obtain enough 200mm capacity in 2021. Ot... » read more

The Darker Side Of Hybrid Bonding

By Katherine Derbyshire - 17 Dec, 2020 - Comments: 2

With semiconductors, it's often things everyone takes for granted that cause the biggest headaches, and that problem is compounded when something fundamental changes — such as bonding two chips together using a process aimed at maximizing performance. Case in point: CMP for backend of the line metallization in hybrid bonding. While this is a mature process, it doesn't easily translate for ... » read more

Adding Value With Unit Level Traceability (ULT) In Automotive Packaging

By Ajay Sattu - 17 Dec, 2020 - Comments: 0

Automotive product traceability has existed in one form or another for several decades. Traceability generally refers to tracking and tracing each component that comprises every sub-system in a car. Traditionally, this has been achieved with direct part marking on mechanical or electronic components, using 1D or 2D barcodes or radio-frequency identification (RFID). Since vehicle recalls are cos... » read more

Wafer Prep Key To Thinning SiP

By Annette Teng - 17 Dec, 2020 - Comments: 0

In its ongoing push to create smaller, thinner, and denser chip packages, the semiconductor industry has intensified its focus on integrating separately manufactured components with different functionalities into systems-in-package (SIPs). Known as heterogeneous integration (HI), this approach now drives the industry’s roadmap for advancement. SiPs enable power-efficient, high-bandwidth conne... » read more

Chip Equipment Billings Soar In 2020

By Clark Tseng - 17 Dec, 2020 - Comments: 0

The global economy has started down a gradual path to recovery from COVID-19 in recent months as the world continues to combat the virus. Yet one sector – semiconductors – has shown impressive growth powered by a transformation hastened by the pandemic across industries ranging from education and work-from-home to healthcare. Semiconductor sales increased 12% in September to mark a secon... » read more

Novel Etch Technologies Utilizing Atomic Layer Process For Advanced Patterning

By TEL - 17 Dec, 2020 - Comments: 0

We demonstrated a high selective and anisotropic plasma etch of Si3N4 and SiC. The demonstrated process consists of a sequence of ion modification and chemical dry removal steps. The Si3N4 etch with H ion modification showed a high selectivity to SiO2 and SiC films. In addition, we have developed selective etch of SiC with N ion modification. On the other hand, in the patterning etch processes,... » read more

Process Variation Analysis of Device Performance Using Virtual Fabrication

By Coventor - 16 Dec, 2020 - Comments: 0

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. W... » read more

AI And High-NA EUV At 3/2/1nm

By Mark LaPedus - 16 Dec, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

New RDL-First PoP Fan-Out Wafer-Level Package Process With Chip-to-Wafer Bonding Technology

By Amkor - 16 Dec, 2020 - Comments: 0

Fan-Out Wafer-Level Interposer Package-on Package (PoP) design has many advantages for mobile applications such as low power consumption, short signal path, small form factor, and heterogeneous integration for multifunctions. In addition, it can be applied in various package platforms, including PoP, System-in-Package (SiP), and Chip Scale Package (CSP). These advantages come from advanced inte... » read more

A Production-Worthy Fan-Out Solution — ASE FOCoS Chip Last

By ASE - 16 Dec, 2020 - Comments: 0

The 5th Generation (5G) wireless systems popularity will push the package development into a high performance and heterogeneous integration form. For high I/O density and high performance packages, the promising Fan Out Chip on Substrate (FOCoS) provides a solution to match outsourced semiconductor assembly and testing (OSAT) capability. FOCoS is identified the Fan Out (FO) package, which can f... » read more

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