What’s Next In AI, Chips And Masks


Aki Fujimura, chief executive of D2S, sat down with Semiconductor Engineering to talk about AI and Moore’s Law, lithography, and photomask technologies. What follows are excerpts of that conversation. SE: In the eBeam Initiative’s recent Luminary Survey, the participants had some interesting observations about the outlook for the photomask market. What were those observations? Fujimur... » read more

A Study Of Wiggling AA Modeling And Its Impact On Device Performance In Advanced DRAM


In this paper, a wiggling active area (fin) in an advanced 1x DRAM process was analyzed and modeled using the pattern-dependent etch simulation capabilities of the SEMulator3D semiconductor modeling software. Nonuniformity in sidewall passivation caused by hard mask pattern density loading was identified as the root cause of the wiggling profile. The calibrated model mimicked these phenomena, g... » read more

FinFETs Give Way To Gate-All-Around


When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As compared to prior planar transistors, the fin, contacted on three sides by the gate, provides much better control of the channel formed within the fin. But, finFETs are already reaching the end of their utility as... » read more

Challenges And Approaches To Developing Automotive Grade 1/0 FCBGA Package Capability


Automotive Grade 1 and 0 package requirements, defined by Automotive Electronics Council (AEC) Document AEC-100, require more severe temperature cycling and high temperature storage conditions to meet harsh automotive field requirements, such as a maximum 150°C device operating temperature, 15-year reliability and zero-defect quality level. Moreover, increased integration of device functionali... » read more

Yield Enhancement Technology: Efforts To Suppress Nanosized Particles In Semiconductor Production Equipment


The currently dominant semiconductor process size is in the range between a few and a few dozen nanometers. That means if a nanosized particle smaller than a virus (hereinafter simply “particle”) is present on a silicon substrate, it could cause a defect in the semiconductor device, lowering the production yield (i.e., the percentage of good chips produced in a manufacturing process). Preve... » read more

Survey: eBeam Initiative Luminaries (formerly Perceptions) Survey Results


Survey of 77 industry luminaries across 42 different companies in July 2020 says net neutral COVID-19 business impact by 2021, with 24% positive vs 20% negative predictions. Click here to view the survey results. » read more

Improving EUV Underlayer Coating Defectivity Using Point-Of-Use Filtration


Authors: Aiwen Wu (Entegris, Inc. — United States), Hareen Bayana (Entegris GmbH — Germany), Philippe Foubert (imec — Belgium), Andrea Chacko and Douglas Guererro (Brewer Science, Inc. — United States). This paper describes efforts to leverage different filtration parameters, including retention ratings and membrane materials, to understand their impact on EUV underlayer coating defe... » read more

Manufacturing Bits: Nov. 17


Intel’s gate-all-around FETs At the upcoming IEEE International Electron Devices Meeting (IEDM), Intel is expected to present papers on its efforts to develop gate-all-around transistors. One paper from Intel describes a more conventional gate-all-around transistor technology called a nanosheet FET. Another paper involves a next-generation NMOS-on-PMOS nanoribbon transistor technology. (F... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Apple has introduced a new MacBook Air, 13-inch MacBook Pro, and Mac mini powered by the M1, the first in a family of chips designed by Apple specifically for the Mac. Based on a 5nm process from TSMC, the M1 is packed with 16 billion transistors, the most Apple has ever put into a chip. It features a CPU core, graphics, AI and other functions all in the same chip. In total... » read more

Challenges Linger For EUV


Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

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