category: Test, Measurement and Analytics

category: IoT, Security & Automotive

Using Analytics To Reduce Burn-in
By Anne Meixner - 12 Jan, 2021 - Comments: 3

Silicon providers are using adaptive test flows to reduce burn-in costs, one of the many approaches aimed at stemming cost increases at advanced nodes and in advanced packages. No one likes it when their cell phone fails within the first month of ownership. But the problems are much more pressing when the key components in data warehouse servers or automobiles fail. Reliability expectations ... » read more

System-Level Test Methodologies Take Center Stage
By Fabio Pizza - 12 Jan, 2021 - Comments: 0

Because electronic systems for all applications in end-user markets must provide the highest possible reliability to match customers’ quality expectations, semiconductor components undergo multiple tests and stress steps to screen out defects that could arise during their lifecycle. Due to new semiconductor devices’ increasing design complexity and extreme process technology, increased test... » read more

Part Average Test (PAT)
By yieldHUB - 12 Jan, 2021 - Comments: 0

With semiconductor manufacturers producing huge amounts of data, it can be hard to guarantee quality and reliability, even with internal tools. Many companies outsource Part Average Testing (PAT) to a bespoke yield management provider. Provided they meet the standards set out by AEC, the tool will be invaluable in guaranteeing quality and reliability for your customers. Click here to con... » read more

Photonic Integration Based On A Ferroelectric Thin-Film Platform
By Advantest - 11 Jan, 2021 - Comments: 0

Photonic-integrated circuits (PICs) using ferroelectric materials are expected to be used in many applications because of its unique optical properties such as large electrooptic coefficients. In this study, a novel PIC based on a ferroelectric thin-film platform was designed and fabricated, where high-speed optical modulator, spot-size converters (SSCs), and a variable optical attenuator (VOA)... » read more

Multi-Layer Deep Data Performance Monitoring And Optimization
By proteanTecs - 11 Jan, 2021 - Comments: 0

Combining functional and parametric monitoring of the real-world behavior of complex SoCs provides a powerful new approach that facilitates performance optimization during development and in the field, improves security and safety, and enables predictive maintenance to prevent field failures. proteanTecs’ Universal Chip Telemetry (UCT) and Siemens’ Tessent Embedded Analytics are complementa... » read more

Full Metrology Solutions For Advanced RF With Picosecond Ultrasonic Metrology
By Onto Innovation - 11 Jan, 2021 - Comments: 0

Picosecond Ultrasonics (PULSE Technology) has been widely used in thin metal film metrology because of its unique advantages, such as being a rapid, non-contact, non-destructive technology and its capabilities for simultaneous multiple layer measurement. Measuring velocity and thickness simultaneously for transparent and semi-transparent films offers a lot of potential for not only monitoring ... » read more

Testing More To Boost Profits
By Anne Meixner - 30 Dec, 2020 - Comments: 0

Not all chips measure up to spec, but as more data becomes available and the cost of these devices continues to rise, there is increasing momentum to salvage and re-purpose chips for other applications and markets. Performance-based binning is as old as color-banded resistors, but the practice is spreading — even for the most advanced nodes and packages. Over the last three decades, engine... » read more

Predicting Reliability At 3/2nm And Beyond
By Ed Sperling - 08 Dec, 2020 - Comments: 0

The chip industry is determined to manufacture semiconductors at 3/2nm — and maybe even beyond — but it's unlikely those chips will be the complex all-in-one SoCs that have defined advanced electronics over the past decade or so. Instead, they likely will be one of many tiles in a system that define different functions, the most important of which are highly specialized for a particular app... » read more

Digital Test Bulks Up – Or Down
By Bryon Moyer - 08 Dec, 2020 - Comments: 2

Large digital integrated circuits are becoming harder to test in a time- and cost-efficient manner. AI chips, in particular, have tiled architectures that are putting pressure on older testing strategies due to the volume of test vectors required. In some cases, these chips are so large that they exceed reticle size, requiring them to be stitched together. New testing efficiencies are needed... » read more

Introduction To Test Data Formats
By Marie Ryan - 08 Dec, 2020 - Comments: 0

This blog is intended to provide an introduction to STDF and ATDF data formats. This is not intended to be definitive, only an introduction. If you are experienced with seeing data in spreadsheets and tables, then STDF is very different from what you are used to. Here we try to explain. STDF is the “Standard Test Data Format” developed jointly between some of the largest test equipment v... » read more

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