Why Silent Data Errors Are So Hard To Find


Cloud service providers have traced the source of silent data errors to defects in CPUs — as many as 1,000 parts per million — which produce faulty results only occasionally and under certain micro-architectural conditions. That makes them extremely hard to find. Silent data errors (SDEs) are random defects produced in manufacturing, not a design bug or software error. Those defects gene... » read more

Yield Is Top Issue For MicroLEDs


MicroLED display makers are marching toward commercialization, with products such as Samsung’s The Wall TV and Apple’s smart watch expected to be in volume production next year or in 2024. These tiny illuminators are the hot new technology in the display world, enabling higher pixel density, better contrast, lower power consumption, and higher luminance in direct sunlight — while consu... » read more

Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues


Bumps are a key component in many advanced packages, but at nanoscale levels making sure all those bumps have a consistent height is an increasing challenge. Without co-planarity, surfaces may not properly adhere. That can reduce yield if the problem is not identified in packaging, or it can cause reliability problems in the field. Identifying those issues requires a variety of process steps... » read more

Heterogeneous Integration: Exposing Large Panels With Fewer Shots


By John Chang, with Corey Shay, James Webb, and Timothy Chang The More than Moore era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration is one tool helping accomplish these gains by combining multiple silicon nodes and designs inside one pac... » read more

Analysis Of Pattern Distortion By Panel Deformation And Addressing It By Using Extremely Large Exposure Field Fine-Resolution Lithography


The growing demand for heterogeneous integration is driven by the 5G market. This includes smartphones, data centers, servers, high-performance computing (HPC), artificial intelligence (AI) and internet of things (IoT) applications. Next-generation packaging technologies require tighter overlay to accommodate larger package sizes with fine-pitch chip interconnects on large-format flexible panel... » read more

The Future Of Connectivity Is Higher Data Rates And Micro-Positioning


These days, we tend to take global wireless connectivity for granted. Whether we’re in a coffee shop, a hotel room, or a plane at 35,000 feet, chances are that we’ll be able to enjoy Internet access at reasonable speeds. But despite this constant connectedness, we still manage to misplace our keys and forget where we left our smartphones. New connectivity technologies are promising to ha... » read more

Quantification Of Steels And Alloys Using A Dual Source Multidetector System On SEM


The accurate and precise analysis of steels and alloys is essential for understanding their mechanical and thermal properties. Such materials often have a wide range of elements at various concentrations down to trace ppm levels. Accordingly, it is not possible to determine the concentrations of all elements with a standard scanning electron microscope (SEM) and an energy dispersive spectromete... » read more

GUC GLink Test Chip Uses In-Chip Monitoring And Deep Data Analytics For High Bandwidth Die-To-Die Characterization


Advanced ASIC leader Global Unichip Corp (GUC) has developed GLink, a high-bandwidth, low-latency, and power-efficient die-to-die (D2D) interface. GLink offers the industry’s highest optimized interconnect solution for both CoWoS and InFO packaging technologies. The GUC and proteanTecs collaboration started with GUC’s second generation of GLink, known as GLink 2.0. The project target was... » read more

The Development Of Front-End Module For 5G Millimeter-Wave Device Testing


This article describes the development of a front-end module for 5G millimeter-wave device testing. 5G millimeter-wave is planned to be used up to the 53 GHz band. Our challenges are to optimize the performance of our test system up to that frequency band including wide power range of EVM performance, and to add a new one-port S-Parameter measurement function. We describe the elemental technolo... » read more

Hunting For Macro Defects: The Importance Of Bare Wafer Inspection


As logic and memory semiconductor devices approach the limits of Moore’s Law, the requirements for accuracy in layer transfer become increasingly stringent. One leading silicon wafer manufacturer estimates that 50% of epitaxial wafer supply for logic will be on nodes equal to or less than 7nm. This is up approximately 30% from earlier in the decade. To meet the demands of extreme ultraviol... » read more

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