How To Improve Yield Ramp For New Designs And Technology Nodes


The complicated silicon defect types and defect distribution of new IC manufacturing technologies can result in very low yield for new designs and technology nodes. During technology qualification using test chips, scan chain failures account for most of the chip failures. Diagnosing those scan chain defects is a powerful way to uncover new and systematic defects. The chip maker’s goal is ... » read more

Automotive Applications Demand Silicon Lifecycle Management


Every electrical engineer learns early in university studies that automobiles are a highly demanding environment for electronics. Temperature and humidity extremes, noise and vibration, electrical interference, exposure to alpha particles, and other factors all make it hard to design and manufacture chips that will operate properly under all conditions. These challenges are exacerbated as chips... » read more

Characterization Of HEMT Vias


The Zeta-Series optical profilers provide accurate measurement and automated analysis of high aspect ratio structures such as HEMT vias using non-destructive and high throughput metrology techniques.  Introduction Wide bandgap semiconductor materials are extremely attractive for use in power electronics, due to their performance capability at high temperature, power and frequency. Among wide... » read more

Bump Height Uniformity And 3D Sensing


Achieving 3D sensing for semiconductor bump height uniformity is essential before adding photoresist. But there are challenges in using traditional methods for measuring uniformity after copper plating, which requires a combination of 3D fringe projection technology and NanoResolution inspection and metrology. Here’s what we’ve learned in a bump height uniformity case study: » read more

Modeling Silicon Photonics Process Parameter Variations In Synopsys OptoCompiler-OptSim


Silicon photonics (SiPh) refers to the enablement of photonic integrated circuits (PIC) over silicon wafer. SiPh enables compatibility with existing CMOS manufacturing infrastructure for large-scale integration and brings the associated benefits to the photonics, namely, lower footprint, lower thermal effects, and co-packaging of electronics and photonics on the same chip. One of the side-effec... » read more

Super-Resolution Microscopy


The enhanced resolving power of super-resolution microscope technology enables the imaging and quantitative analysis of cellular dynamics and nanostructures that were previously inaccessible. Download this eBook to learn about: Principles and advantages of super-resolution microscopy (SRM) for life sciences research. Problems solved by SRM Common approaches to achieving be... » read more

Simplifying The Path From Design To Test


By Richard Fanning and John Rowe Getting an integrated circuit (IC) from design to test is an arduous process that encompasses a number of steps, including: Design for Test (DFT): processes that ensure the chip is designed in such a way that it can be tested Development: the development of automated test programs (ATPs) Bench: evaluating the device at the bench to ensure the desig... » read more

Test Connections Clean Up With Real-Time Maintenance


Test facilities are beginning to implement real-time maintenance, rather than scheduled maintenance, to reduce manufacturing costs and boost product yield. Adaptive cleaning of probe needles and test sockets can extend equipment lifetimes and reduce yield excursions. The same is true for load board repair, which is moving toward predictive maintenance. But this change is much more complicate... » read more

Automated Optical Inspection


Building good automated models for inspection require more data to be collected, both good and bad. Vijay Thangamariappan, R&D engineer at Advantest, explains how to develop models for automating optical inspection, using a multi-thousand pin socket as an example for how machine learning has helped reduce the return rate due to defects from 2% down to zero. He also explains how to achieve t... » read more

Optimizing Vmin With Path Margin Monitors


By Firooz Massoudi and Ash Patel Choosing the right operating voltage for various digital blocks within a semiconductor device is one of the most important tasks faced by chip designers. Operating voltage has major effects on performance, power consumption, and reliability. Increasing the voltage generally increases performance, but at the cost of more power and higher lifetime operating cos... » read more

← Older posts Newer posts →