Capturing Performance


The challenge of working out the best performance for a given power budget is not a new one, but in many power-sensitive applications, the balance is tricky and requires sophisticated techniques. This is especially true in the media processor market where many systems companies are held back by power, energy and thermal issues. “It's really not a battery problem, it's a thermal problem... » read more

Accelerating Development For LP


Power is a limiting factor in all devices these days, and while most of the industry has seen this coming for several process nodes and a succession of mobile devices with limited battery life, the power problem remains a work in progress. No matter how much progress is made—and there has been plenty of work done in the areas of multiple power domains, dark silicon, dynamic voltage and fr... » read more

Power Management Verification Requires Holistic Approach


Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

One-On-One: Dark Possibilities


Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. (P... » read more

One-On-One: Dark Servers


Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. To... » read more

Stacked Die, Phase Two


The initial hype phase of [getkc id="82" kc_name="2.5D"] appears to be over. There are multiple offerings in development or on the market already from Xilinx, Altera, Cisco, Huawei, IBM, AMD, all focused on better throughput over shorter distances with better yield and lower power. Even Intel has jumped on the bandwagon, saying that 2.5D will be essential for extending [getkc id="74" comment="M... » read more

The Wild West Of Automotive


Automotive is considered one of the great new markets for EDA and IP. Electronic complexity is increasing rapidly, product update cycles are decreasing, and new standards mean that many of the old ways of doing development are no longer possible. Such change creates opportunity, along with a certain degreed of confusion. As the number of discrete systems increases, so do costs. Electronics c... » read more

One-On-One: Dark Silicon


Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. (F... » read more

UPF 3.0 Moves Toward Ratification


[gettech id="31044" t_name="UPF"] (Unified Power Format) 3.0 — the fourth incarnation in 10 years — is moving closer to the IEEE ballot process. Erich Marschner, verification architect at [getentity id="22017" e_name="Mentor Graphics"] and vice chair of the [gettech id="31043" comment="IEEE 1801"] working group, explained the working group is as close as possible to being on schedule for... » read more

Is Dark Silicon Wasted Silicon?


The concept of dark silicon sounds almost mysterious, but it is a simple matter of physics. With advances in technology nodes and the ability to pack more and more transistors on the same die, design engineers are reaching a wall where only a fraction of a design can be powered on due to power and thermal implications. Moreover, the challenges that force this kind of complex power managemen... » read more

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