category: Top Stories

category: Auto, Security & Edge AI

Synthesizing Hardware From Software
By Brian Bailey - 22 Aug, 2019 - Comments: 1

The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible. While high-level synthesis (HLS) did come out of this work and has proven to be... » read more

What Is A Custom Processor?
By Ann Mutschler - 22 Aug, 2019 - Comments: 2

Spurred by the latest cyclical development boom, the semiconductor industry is entering a new golden era of custom processors, but this time ‘custom processor’ means something different. A generation ago, every major semiconductor company had in-house processors: SuperH, PowerPC, V800, Alpha, MEP, Trimedia, etc., with some specializing more than others for particular domains. But industr... » read more

Chiplets, Faster Interconnects, More Efficiency
By Ed Sperling - 22 Aug, 2019 - Comments: 1

Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency. Taken as a whole, this represents a significant shift in direction for the major chip companies. All of them are wrestling with massive increases in processing demands ... » read more

Siemens-Mentor Deal Retrospective
By Ed Sperling - 21 Aug, 2019 - Comments: 1

Tony Hemmelgarn, president and CEO of Siemens PLM Software and CEO of Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about the acquisition of Mentor Graphics, the shift toward more customized design, and where AI fits into the design picture. SE: How does a company like Siemens see the EDA industry evolving? Hemmelgarn: Part of the reason we bought Mentor Grap... » read more

Debug Tools Are Improving
By Brian Bailey - 12 Aug, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss debugging complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. Part one can be found here. Part two... » read more

Are Digital Twins Something For EDA To Pursue?
By Ann Mutschler - 07 Aug, 2019 - Comments: 0

‘Digital Twins’ are one of the new, fashionable key concepts for system developers, but do they fit with EDA? How many different types of engines do these twins run on – abstract simulation, signal-based RTL simulation, emulation, prototyping, actual silicon? What should the use models be called for digital twinning – like reproduction of bugs from silicon in emulation? Or optimizing th... » read more

Hardware-Software Co-Design Reappears
By Brian Bailey - 25 Jul, 2019 - Comments: 1

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on. What's different this time around is the growing complexity and an emphasis on architectural improvements, as well as device scaling, particularly for AI/ML applications. Software is a critical component, and the more tightly integrate... » read more

Hybrid Emulation Takes Center Stage
By Ann Mutschler - 25 Jul, 2019 - Comments: 0

From mobile to networking to AI applications, system complexity shows no sign of slowing. These designs, which may contain multiple billion gates, must be validated, verified and tested, and it’s no longer possible to just throw the whole thing in a hardware emulator. For some time, emulation, FPGA-based prototyping, and virtual environments such as simulators have given design and verific... » read more

How To Optimize Verification
By Brian Bailey - 25 Jul, 2019 - Comments: 0

The rate of improvement in verification tools and methodologies has been nothing short of staggering, but that has created new kinds of problems for verification teams. Over the past 20 years, verification has transformed from a single language (Verilog) and tool (simulator) to utilizing many languages (testbench languages, assertion languages, coverage languages, constraint languages), many... » read more

Partitioning Drives Architectural Considerations
By Ann Mutschler - 19 Jul, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence; Mark Olen, product marketing group manager at Mentor, a Siemens Business; Tom Anderson, technical mar... » read more

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