SAP: A Secure Low-Latency Protocol for Mitigating High Computation Overhead in WI-FI Networks


The increase in popularity of wireless networks in industrial, embedded, medical and public sectors has made them an appealing attack surface for attackers who exploit the vulnerabilities in network protocols to launch attacks such as Evil Twin, Man-in-the-middle, sniffing, etc., which may result in economic and non-economic losses. To protect wireless networks against such attacks, IEEE 802.11... » read more

Arm Statistical Profiling Extension: Performance Analysis Methodology


This paper presents a methodology for workload characterization and root cause analysis using the Arm Statistical Profiling Extension (SPE) demonstrated on a Neoverse N1 core. The target audience are software developers and performance analysts in software development, analysis, optimization, and tuning. This paper may also help silicon engineers to conduct performance analysis and debugging. T... » read more

Demystifying Mixed-Signal Simulation For Digital Verification Engineers


The convergence of analog and digital technologies on a single chip, commonly referred to as mixed-signal, has reshaped the integrated circuit (IC) landscape. In recent years, mixed-signal designs have emerged as the dominant technology, therefore requiring traditional analog and digital methodologies to be enhanced. A mixed-signal design offers many advantages, including boosted performance, r... » read more

HBM3 Memory: Break Through to Greater Bandwidth


Delivering unrivaled memory bandwidth in a compact, high-capacity footprint, has made HBM the memory of choice for AI/ML and other high-performance computing workloads. HBM3 as the latest generation of the standard raises data rates to 6.4 Gb/s and promises to scale even higher. The Rambus HBM3 controller provides industry-leading support of the extended roadmap for HBM3 with performance to 9.6... » read more

Using Keysight Design Data Management SOS In The Cloud


Integrated circuits (ICs) are becoming increasingly complex and resource intensive. This is challenging companies to design chips more efficiently and reduce the overall impact of peak processing loads. Companies typically use large server farms and high-performance storage systems to design and validate chips quickly and efficiently. However, this approach is very resource intensive. For ex... » read more

Achieving High-Performance, Low-Power Design Optimization With The Solido Library IP Solution


Achieving overall power, performance, and area (PPA) targets is a key goal for today’s advanced IC design projects. To accomplish this, standard cell and memory libraries must be optimized for PPA. In this white paper, we describe how the Siemens Solido IP Library Solution helps engineering teams design and verify library IP to optimize PPA tradeoffs, maximize yield, and validate for easy int... » read more

Using In-Chip Monitoring And Deep Data Analytics For High Bandwidth Memory (HBM) Reliability And Safety


Since its introduction in 2014, High Bandwidth Memory (HBM) has been poised to address the growing demand for high-performance, high capacity, and low latency memories required by High-Performance Computing (HPC), high-performance graphic processors (GPU), and artificial intelligence (AI). Since then, bandwidth and capacity requirements have increased with each new generation: HBM2, HBM2e and n... » read more

Leveraging IBIS-AMI Models To Optimize PCIe 6.0 Designs


The exploding demand for more data driven by advancements such as artificial intelligence and machine learning has created an increase in bandwidth (BW) for interconnects for different systems and hardware components such as graphic cards, network cards, storge devices, CPUs, memories, and many more. PCIe is the leading high-speed serial communication protocol for connecting such hardware compo... » read more

Fluid Dispensing For Packaging Today’s Devices


Fluid dispensing systems are evolving in order to address the challenges that system-in-package (SiP) and micromechanical systems (MEMS) packages face, especially in regard to tight geometries and assembly processes. These packages, used in smartphones, have become more miniaturized, and as a result, have created added value in the market. However, they include a variety of small dies or dev... » read more

Use Advanced DFT And Silicon Bring Up To Accelerate AI Chip Design


The market for AI chips is growing quickly, with the 2022 revenue of $20B expected to grow to over $300B by 2030. To keep up with the demand and stay competitive, AI chip designers set aggressive time-to-market goals. Design teams looking for ways to shave significant time off chip development time can look to advanced DFT and silicon bring up techniques described in this paper, including hiera... » read more

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