Building A Robust Hardware Security Program


Even mature chip development teams and processes aren’t immune to security errors. While many semiconductor and hardware manufacturing organizations have mature development processes, existing security testing practices, and formal signoff requirements, the complexity and duration of the chip lifecycle creates many opportunities for security issues to be overlooked. Semiconductors now play... » read more

Kria KR260 Robotics Starter Kit: Unleashing Roboticists Through Hardware Acceleration


The Kria™ KR260 Robotics Starter Kit is a Kria SOM-based development platform for robotics and factory automation applications. It enables roboticists and industrial developers without FPGA expertise to develop hardware accelerated applications for robotics, machine vision, industrial communications and control. Developers benefit with greater flexibility from native ROS 2 (Humble Hawksb... » read more

High-Level Synthesis: It’s Still Hardware Design


Hardware design using HLS is no different than the typical ASIC/FPGA design flow with the exception that C++/SystemC is being used along with HLS to create the RTL instead of hand coding it. The advantage of using HLS is that it speeds up RTL creation time and reduces verification time by producing bug free RTL quickly from a fully verified C++/SystemC source. The misconception that still exist... » read more

Zone-ECU Virtualization Solution Platform


The high complexity of future vehicle systems will need to move away from today’s distributed automotive E/E architecture towards a more centralized E/E structure based on less but much more powerful ECUs, instead of many individual control entities. A Zone-oriented architecture moves the integration of numerous functions and services into one ECU. The resulting network concept must deal w... » read more

Designing Application-Specific Processors for Wireless 5G SoCs


Traditional architectures for wireless baseband applications are no longer adequate for recent and next-generation modem standards. Supporting complex and still evolving standards like 5G in a single modem is only possible by using SDR techniques, which place increasing demands on performance and power consumption on the SoC. ASIP architectures enable full customization of a processor, which... » read more

Evolving Your ADAS And AV Tests With Emulation Capability


Creating safe and robust autonomous driving (AD) systems is a complex task. Autonomous vehicles (AVs) have hundreds of sensors, all of which need to work with one another inside the car and with other smart vehicles. The software algorithms enabling autonomous driving features will ultimately need to synthesize all the information collected from these sensors to ensure that the vehicle responds... » read more

EDA Software Design Flow Considerations For The RF/Microwave Module Designer


Miniaturization of consumer products, aerospace and defense systems, medical devices, and LED arrays has spawned the development of a technology known as the multi-chip module (MCM), which combines multiple integrated circuits (ICs), semiconductor die, and other discrete components within a unifying substrate for use as a single component. This white paper outlines the steps for implementing an... » read more

A Guide To Fast Optimal Solutions To Complex Problems For Quantum Computers


Most people have already heard the term “quantum computer.” There has been a lot of interest in quantum computers over the last few years, with great expectations that they will dramatically change the world soon. These days, we use computers all the time in our daily lives. Personal computers and smartphones are obvious computers, but there are many more computers hidden in plain sight aro... » read more

Wafer Level Void-Free Molded Underfill For High-Density Fan-out Packages


In this study, experiments and mold flow simulation results are presented for a void-free wafer level molded underfill (WLMUF) process with High-Density Fan-Out (HDFO) test vehicles using a wafer-level compression molding process. The redistribution layer (RDL)-first technology was applied with 3 layers of a fine-pitch RDL structure. The test samples comprised 11.5 x 12.5-mm2 die with tall copp... » read more

Study Of Bondable Laser Release Material Using 355nm Energy To Facilitate RDL-First And Die-First Fan-Out Wafer-Level Packaging (FOWLP)


A thorough evaluation on selecting a bondable laser release material for redistribution layer (RDL)-first and die-first fan-out wafer-level packaging (FOWLP) is presented in this article. Four laser release materials were identified based on their absorption coefficient at 355 nm. In addition, all four of these materials possess thermal stability above 350 °C and pull-off adhesion on a Ti/Cu l... » read more

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